Ravi Varadarajan

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of global design closure at top level and driving of downstr...
- Patent number 8,839,171
- Issue date Sep 16, 2014
- Atrenta, Inc.
- Ravi Varadarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient method to analyze RTL structures that cause physical impl...
- Patent number 8,782,582
- Issue date Jul 15, 2014
- Atrenta, Inc.
- Jitendra Gupta
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method for creating physical connections in 3D integrated circuits
- Patent number 8,732,647
- Issue date May 20, 2014
- Atrenta, Inc.
- Lenuta Georgeta Claudia Rusu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus representation for efficient physical synthesis of integrated c...
- Patent number 7,451,427
- Issue date Nov 11, 2008
- Atrenta, Inc.
- Ravi Varadarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized placement and routing of datapaths
- Patent number 5,838,583
- Issue date Nov 17, 1998
- Cadence Design Systems, Inc.
- Ravi Varadarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual interface representation of hierarchical symbolic layouts
- Patent number 5,604,680
- Issue date Feb 18, 1997
- Cadence Design Systems, Inc.
- Cyrus Bamji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying overconstraints using port abstraction graphs
- Patent number 5,581,474
- Issue date Dec 3, 1996
- Cadence Design Systems, Inc.
- Cyrus Bamji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying overconstraints using port abstraction graphs
- Patent number 5,568,396
- Issue date Oct 22, 1996
- Cadence Design Systems, Inc.
- Cyrus Bamji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hier archical pitchmaking compaction method and system for integrat...
- Patent number 5,381,343
- Issue date Jan 10, 1995
- Cadence Design Systems, Inc.
- Cyrus Bamji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cloning method and system for hierarchical compaction
- Patent number 5,281,558
- Issue date Jan 25, 1994
- Cadence Design Systems, Inc.
- Cyrus S. Bamji
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF GLOBAL DESIGN CLOSURE AT TOP LEVEL AND DRIVING OF DOWNSTR...
- Publication number 20140298281
- Publication date Oct 2, 2014
- ATRENTA, INC.
- Ravi Varadarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUS REPRESENTATION FOR EFFICIENT PHYSICAL SYNTHESIS OF INTEGRATED C...
- Publication number 20060282800
- Publication date Dec 14, 2006
- ATRENTA, INC.
- Ravi Varadarajan
- G06 - COMPUTING CALCULATING COUNTING

Ravi Varadarajan

Person

Patents Grantslast 30 patents

Method of global design closure at top level and driving of downstr...

Efficient method to analyze RTL structures that cause physical impl...

Method for creating physical connections in 3D integrated circuits

Bus representation for efficient physical synthesis of integrated c...

Optimized placement and routing of datapaths

Virtual interface representation of hierarchical symbolic layouts

Identifying overconstraints using port abstraction graphs

Identifying overconstraints using port abstraction graphs

Hier archical pitchmaking compaction method and system for integrat...

Cloning method and system for hierarchical compaction

Patents Applicationslast 30 patents

METHOD OF GLOBAL DESIGN CLOSURE AT TOP LEVEL AND DRIVING OF DOWNSTR...

BUS REPRESENTATION FOR EFFICIENT PHYSICAL SYNTHESIS OF INTEGRATED C...