Ravikanth Suravarapu

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Austin, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Programmable power combiner and splitter
- Patent number 10,742,176
- Issue date Aug 11, 2020
- MediaTek Singapore Pte Ltd.
- Ravikanth Venkata Suravarapu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low noise, programmable gain current buffer
- Patent number 9,407,296
- Issue date Aug 2, 2016
- Mediatek Inc.
- Saravanan Rajapandian
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Receiver arrangement and method of performing operations of receiver
- Patent number 9,300,264
- Issue date Mar 29, 2016
- MediaTek Inc.
- Ravikanth Suravarapu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
False lock detection mechanism for use in a delay locked loop circuit
- Patent number 7,733,138
- Issue date Jun 8, 2010
- Silicon Laboratories, Inc.
- Gregory T. Uehara
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMABLE POWER COMBINER AND SPLITTER
- Publication number 20190149104
- Publication date May 16, 2019
- MEDIATEK SINGAPORE PTE. LTD.
- Ravikanth Venkata Suravarapu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW NOISE, PROGRAMMABLE GAIN CURRENT BUFFER
- Publication number 20160164546
- Publication date Jun 9, 2016
- MEDIATEK INC.
- Saravanan Rajapandian
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOW NOISE, PROGRAMMABLE GAIN CURRENT BUFFER
- Publication number 20160056784
- Publication date Feb 25, 2016
- MEDIATEK INC.
- Saravanan Rajapandian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
False lock detection mechanism for use in a delay locked loop circuit
- Publication number 20070057708
- Publication date Mar 15, 2007
- Gregory T. Uehara
- H03 - BASIC ELECTRONIC CIRCUITRY