Ravindra Nath Bhargava

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic page state aware scheduling of read/write burst transactions
- Patent number 12,282,439
- Issue date Apr 22, 2025
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Staging memory access requests
- Patent number 12,253,961
- Issue date Mar 18, 2025
- Advanced Micro Devices, Inc.
- James R. Magro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with hybrid DRAM/persistent memory channel arbitr...
- Patent number 11,995,008
- Issue date May 28, 2024
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to efficiently rinse memory-side cache of dirty data
- Patent number 11,874,774
- Issue date Jan 16, 2024
- Advanced Micro Devices, Inc.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Region based directory scheme to adapt to large cache sizes
- Patent number 11,809,322
- Issue date Nov 7, 2023
- Advanced Micro Devices, Inc.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient and low latency memory access scheduling
- Patent number 11,789,655
- Issue date Oct 17, 2023
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient and low latency memory access scheduling
- Patent number 11,782,640
- Issue date Oct 10, 2023
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient rank switching in multi-rank memory controller
- Patent number 11,755,246
- Issue date Sep 12, 2023
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM command streak efficiency management
- Patent number 11,687,281
- Issue date Jun 27, 2023
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM command streak management
- Patent number 11,625,352
- Issue date Apr 11, 2023
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive page close prediction
- Patent number 11,526,278
- Issue date Dec 13, 2022
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative hint-triggered activation of pages in memory
- Patent number 11,429,281
- Issue date Aug 30, 2022
- Advanced Micro Devices, Inc.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Region based directory scheme to adapt to large cache sizes
- Patent number 11,119,926
- Issue date Sep 14, 2021
- Advanced Micro Devices, Inc.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic page state aware scheduling of read/write burst transactions
- Patent number 10,846,253
- Issue date Nov 24, 2020
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative hint-triggered activation of pages in memory
- Patent number 10,613,764
- Issue date Apr 7, 2020
- Advanced Micro Devices, Inc.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache control aware memory controller
- Patent number 10,572,389
- Issue date Feb 25, 2020
- Advanced Micro Devices, Inc.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tag accelerator for low latency DRAM cache
- Patent number 10,545,875
- Issue date Jan 28, 2020
- Advanced Micro Devices, Inc.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache to cache data transfer acceleration techniques
- Patent number 10,503,648
- Issue date Dec 10, 2019
- Advanced Micro Devices, Inc.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic per-bank and all-bank refresh
- Patent number 10,503,670
- Issue date Dec 10, 2019
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread selection at a processor based on branch prediction confidence
- Patent number 10,223,124
- Issue date Mar 5, 2019
- Advanced Micro Devices, Inc.
- Ramkumar Jayaseelan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable distance bypass between tag array and data array pipelines...
- Patent number 9,529,720
- Issue date Dec 27, 2016
- Advanced Micro Devices, Inc.
- Marius Evers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetching to a cache based on buffer fullness
- Patent number 8,909,866
- Issue date Dec 9, 2014
- Advanced Micro Devices, Inc.
- John Kalamatianos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch history with polymorphic indirect branch information
- Patent number 8,782,384
- Issue date Jul 15, 2014
- Advanced Micro Devices, Inc.
- David Suggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting branch direction and target address pattern and supplying...
- Patent number 8,667,257
- Issue date Mar 4, 2014
- Advanced Micro Devices, Inc.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EFFICIENT RANK SWITCHING IN MULTI-RANK MEMORY CONTROLLER
- Publication number 20240069811
- Publication date Feb 29, 2024
- ADVANCED MICRO DEVICES, INC.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT RANK SWITCHING IN MULTI-RANK MEMORY CONTROLLER
- Publication number 20220413759
- Publication date Dec 29, 2022
- ADVANCED MICRO DEVICES, INC.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER WITH HYBRID DRAM/PERSISTENT MEMORY CHANNEL ARBITR...
- Publication number 20220405214
- Publication date Dec 22, 2022
- ADVANCED MICRO DEVICES, INC.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE HINT-TRIGGERED ACTIVATION OF PAGES IN MEMORY
- Publication number 20220404978
- Publication date Dec 22, 2022
- ADVANCED MICRO DEVICES, INC.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM COMMAND STREAK EFFICIENCY MANAGEMENT
- Publication number 20220317928
- Publication date Oct 6, 2022
- ADVANCED MICRO DEVICES, INC.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT AND LOW LATENCY MEMORY ACCESS SCHEDULING
- Publication number 20220317924
- Publication date Oct 6, 2022
- ADVANCED MICRO DEVICES, INC.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT AND LOW LATENCY MEMORY ACCESS SCHEDULING
- Publication number 20220317934
- Publication date Oct 6, 2022
- ADVANCED MICRO DEVICES, INC.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO EFFICIENTLY RINSE MEMORY-SIDE CACHE OF DIRTY DATA
- Publication number 20220091991
- Publication date Mar 24, 2022
- ADVANCED MICRO DEVICES, INC.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGION BASED DIRECTORY SCHEME TO ADAPT TO LARGE CACHE SIZES
- Publication number 20210406180
- Publication date Dec 30, 2021
- ADVANCED MICRO DEVICES, INC.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM COMMAND STREAK MANAGEMENT
- Publication number 20210390071
- Publication date Dec 16, 2021
- ADVANCED MICRO DEVICES, INC.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT MEMORY BUS MANAGEMENT
- Publication number 20210357336
- Publication date Nov 18, 2021
- ADVANCED MICRO DEVICES, INC.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STAGING BUFFER ARBITRATION
- Publication number 20210200694
- Publication date Jul 1, 2021
- ADVANCED MICRO DEVICES, INC.
- JAMES R. MAGRO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STAGING MEMORY ACCESS REQUESTS
- Publication number 20210200695
- Publication date Jul 1, 2021
- ADVANCED MICRO DEVICES, INC.
- JAMES R. MAGRO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PAGE STATE AWARE SCHEDULING OF READ/WRITE BURST TRANSACTIONS
- Publication number 20210073152
- Publication date Mar 11, 2021
- ADVANCED MICRO DEVICES, INC.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE HINT-TRIGGERED ACTIVATION OF PAGES IN MEMORY
- Publication number 20200401321
- Publication date Dec 24, 2020
- ADVANCED MICRO DEVICES, INC.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG ACCELERATOR FOR LOW LATENCY DRAM CACHE
- Publication number 20190196974
- Publication date Jun 27, 2019
- Advanced Micro Devices, Inc.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PER-BANK AND ALL-BANK REFRESH
- Publication number 20190196987
- Publication date Jun 27, 2019
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PAGE STATE AWARE SCHEDULING OF READ/WRITE BURST TRANSACTIONS
- Publication number 20190196995
- Publication date Jun 27, 2019
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE PAGE CLOSE PREDICTION
- Publication number 20190196720
- Publication date Jun 27, 2019
- Advanced Micro Devices, Inc.
- Guanhao Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY DETERMINING MEMORY ACCESS BURST LENGTH
- Publication number 20190196996
- Publication date Jun 27, 2019
- Advanced Micro Devices, Inc.
- Kedarnath Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGION BASED DIRECTORY SCHEME TO ADAPT TO LARGE CACHE SIZES
- Publication number 20190188137
- Publication date Jun 20, 2019
- Advanced Micro Devices, Inc.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE TO CACHE DATA TRANSFER ACCELERATION TECHNIQUES
- Publication number 20190179758
- Publication date Jun 13, 2019
- Advanced Micro Devices, Inc.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE CONTROL AWARE MEMORY CONTROLLER
- Publication number 20190179760
- Publication date Jun 13, 2019
- Advanced Micro Devices, Inc.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE HINT-TRIGGERED ACTIVATION OF PAGES IN MEMORY
- Publication number 20190155516
- Publication date May 23, 2019
- Advanced Micro Devices, Inc.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE DISTANCE BYPASS BETWEEN TAG ARRAY AND DATA ARRAY PIPELINES...
- Publication number 20140365729
- Publication date Dec 11, 2014
- Marius Evers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD SELECTION AT A PROCESSOR BASED ON BRANCH PREDICTION CONFIDENCE
- Publication number 20140201507
- Publication date Jul 17, 2014
- Advanced Micro Devices, Inc.
- Ramkumar Jayaseelan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCHING TO A CACHE BASED ON BUFFER FULLNESS
- Publication number 20140129772
- Publication date May 8, 2014
- Advanced Micro Devices, Inc.
- John Kalamatianos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPLAY OF DETECTED PATTERNS IN PREDICTED INSTRUCTIONS
- Publication number 20120117362
- Publication date May 10, 2012
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH HISTORY WITH POLYMORPHIC INDIRECT BRANCH INFORMATION
- Publication number 20090164766
- Publication date Jun 25, 2009
- David Suggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL PREDICTION OF MULTIPLE BRANCHES
- Publication number 20080209190
- Publication date Aug 28, 2008
- Advanced Micro Devices, Inc.
- Ravindra N. Bhargava
- G06 - COMPUTING CALCULATING COUNTING

Ravindra Nath Bhargava

Person

Patents Grantslast 30 patents

Dynamic page state aware scheduling of read/write burst transactions

Staging memory access requests

Memory controller with hybrid DRAM/persistent memory channel arbitr...

Mechanism to efficiently rinse memory-side cache of dirty data

Region based directory scheme to adapt to large cache sizes

Efficient and low latency memory access scheduling

Efficient and low latency memory access scheduling

Efficient rank switching in multi-rank memory controller

DRAM command streak efficiency management

DRAM command streak management

Adaptive page close prediction

Speculative hint-triggered activation of pages in memory

Region based directory scheme to adapt to large cache sizes

Dynamic page state aware scheduling of read/write burst transactions

Speculative hint-triggered activation of pages in memory

Cache control aware memory controller

Tag accelerator for low latency DRAM cache

Cache to cache data transfer acceleration techniques

Dynamic per-bank and all-bank refresh

Thread selection at a processor based on branch prediction confidence

Variable distance bypass between tag array and data array pipelines...

Prefetching to a cache based on buffer fullness

Branch history with polymorphic indirect branch information

Detecting branch direction and target address pattern and supplying...

Patents Applicationslast 30 patents

EFFICIENT RANK SWITCHING IN MULTI-RANK MEMORY CONTROLLER

EFFICIENT RANK SWITCHING IN MULTI-RANK MEMORY CONTROLLER

MEMORY CONTROLLER WITH HYBRID DRAM/PERSISTENT MEMORY CHANNEL ARBITR...

SPECULATIVE HINT-TRIGGERED ACTIVATION OF PAGES IN MEMORY

DRAM COMMAND STREAK EFFICIENCY MANAGEMENT

EFFICIENT AND LOW LATENCY MEMORY ACCESS SCHEDULING

EFFICIENT AND LOW LATENCY MEMORY ACCESS SCHEDULING

MECHANISM TO EFFICIENTLY RINSE MEMORY-SIDE CACHE OF DIRTY DATA

REGION BASED DIRECTORY SCHEME TO ADAPT TO LARGE CACHE SIZES

DRAM COMMAND STREAK MANAGEMENT

EFFICIENT MEMORY BUS MANAGEMENT

STAGING BUFFER ARBITRATION

STAGING MEMORY ACCESS REQUESTS

DYNAMIC PAGE STATE AWARE SCHEDULING OF READ/WRITE BURST TRANSACTIONS

SPECULATIVE HINT-TRIGGERED ACTIVATION OF PAGES IN MEMORY

TAG ACCELERATOR FOR LOW LATENCY DRAM CACHE

DYNAMIC PER-BANK AND ALL-BANK REFRESH

DYNAMIC PAGE STATE AWARE SCHEDULING OF READ/WRITE BURST TRANSACTIONS

ADAPTIVE PAGE CLOSE PREDICTION

DYNAMICALLY DETERMINING MEMORY ACCESS BURST LENGTH

REGION BASED DIRECTORY SCHEME TO ADAPT TO LARGE CACHE SIZES

CACHE TO CACHE DATA TRANSFER ACCELERATION TECHNIQUES

CACHE CONTROL AWARE MEMORY CONTROLLER

SPECULATIVE HINT-TRIGGERED ACTIVATION OF PAGES IN MEMORY

VARIABLE DISTANCE BYPASS BETWEEN TAG ARRAY AND DATA ARRAY PIPELINES...

THREAD SELECTION AT A PROCESSOR BASED ON BRANCH PREDICTION CONFIDENCE

PREFETCHING TO A CACHE BASED ON BUFFER FULLNESS

REPLAY OF DETECTED PATTERNS IN PREDICTED INSTRUCTIONS

BRANCH HISTORY WITH POLYMORPHIC INDIRECT BRANCH INFORMATION

PARALLEL PREDICTION OF MULTIPLE BRANCHES