RAVISHANKAR RAJARAO

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Bangalore, IN

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Patents Grantslast 30 patents

Information Patent Grant
Bus transaction monitoring and debugging system using FPGA
- Patent number 9,176,839
- Issue date Nov 3, 2015
- Whizchip Design Technologies Pvt. Ltd.
- Ravishankar Rajarao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for creating an executable verification plan
- Patent number 8,938,707
- Issue date Jan 20, 2015
- Whizchip Design Technologies Pvt. Ltd.
- Vishwarao Tadagalale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for providing a random sequence coverage
- Patent number 8,751,870
- Issue date Jun 10, 2014
- Whizchip Design Technologies Pvt. Ltd.
- Ravishankar Rajarao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for test vector generation
- Patent number 8,661,305
- Issue date Feb 25, 2014
- Ravishankar Rajarao
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR PROVIDING A RANDOM SEQUENCE COVERAGE
- Publication number 20130067280
- Publication date Mar 14, 2013
- WhizChip Design Technologies Pvt. Ltd.
- RAVISHANKAR RAJARAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUS TRANSACTION MONITORING AND DEBUGGING SYSTEM USING FPGA
- Publication number 20130013969
- Publication date Jan 10, 2013
- WhizChip Design Technologies Pvt. Ltd.
- RAVISHANKAR RAJARAO
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR TEST VECTOR GENERATION
- Publication number 20130014066
- Publication date Jan 10, 2013
- WhizChip Design Technologies Pvt. Ltd.
- RAVISHANKAR RAJARAO
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR CREATING AN EXECUTABLE VERIFICATION PLAN
- Publication number 20130014077
- Publication date Jan 10, 2013
- WhizChip Design Technologies Pvt. Ltd.
- VISHWARAO TADAGALALE
- G06 - COMPUTING CALCULATING COUNTING