Raymond Bertram

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for determination of a horizontal minimum of digi...
- Patent number 8,650,232
- Issue date Feb 11, 2014
- Via Technologies, Inc.
- Rochelle L. Stortz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of using common adder circuitry for both a horizo...
- Patent number 8,386,545
- Issue date Feb 26, 2013
- Via Technologies, Inc.
- Rochelle L. Stortz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with selective substrate biasing for clock-gated fun...
- Patent number 7,978,001
- Issue date Jul 12, 2011
- Via Technologies, Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Microprocessor with substrate bias clamps
- Patent number 7,920,019
- Issue date Apr 5, 2011
- Via Technologies, Inc.
- Raymond A. Bertram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Data bus inversion detection mechanism
- Patent number 7,668,988
- Issue date Feb 23, 2010
- VIA Technologies, Inc.
- Raymond A. Bertram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N-domino output latch
- Patent number 7,417,465
- Issue date Aug 26, 2008
- VIA Technologies, Inc.
- James R. Lundberg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Accelerated P-channel dynamic register
- Patent number 7,382,161
- Issue date Jun 3, 2008
- VIA Technologies, Inc.
- James R. Lundberg
- G11 - INFORMATION STORAGE
Information Patent Grant
Inverting dynamic register with data-dependent hold time reduction...
- Patent number 7,358,775
- Issue date Apr 15, 2008
- VIA Technologies, Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Accelerated N-channel dynamic register
- Patent number 7,348,806
- Issue date Mar 25, 2008
- VIA Technologies, Inc.
- James R. Lundberg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
P-domino register with accelerated non-charge path
- Patent number 7,321,243
- Issue date Jan 22, 2008
- VIA Technologies, Inc.
- Imran Qureshi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
N-domino register with accelerated non-discharge path
- Patent number 7,317,339
- Issue date Jan 8, 2008
- VIA Technologies, Inc.
- Imran Qureshi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-inverting domino register
- Patent number 7,193,445
- Issue date Mar 20, 2007
- IP First, LLC
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
P-domino register
- Patent number 7,187,210
- Issue date Mar 6, 2007
- VIA Technologies, Inc.
- James R. Lundberg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
P-domino output latch
- Patent number 7,187,211
- Issue date Mar 6, 2007
- VIA Technologies, Inc.
- James R. Lundberg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-inverting domino register
- Patent number 7,187,209
- Issue date Mar 6, 2007
- VIA Technologies, Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimization of clock network capacitance on an integrated circuit
- Patent number 7,131,083
- Issue date Oct 31, 2006
- IP First, LLC
- Raymond Bertram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic multi-input priority multiplexer
- Patent number 7,075,354
- Issue date Jul 11, 2006
- VIA Technologies, Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
P-domino output latch with accelerated evaluate path
- Patent number 7,064,584
- Issue date Jun 20, 2006
- VIA Technologies, Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
N-domino output latch with accelerated evaluate path
- Patent number 7,034,578
- Issue date Apr 25, 2006
- VIA Technologies, Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Complementary input dynamic logic for complex logic functions
- Patent number 6,828,827
- Issue date Dec 7, 2004
- IP First, LLC
- Mir Azam
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD OF USING COMMON ADDER CIRCUITRY FOR BOTH A HORIZO...
- Publication number 20110099214
- Publication date Apr 28, 2011
- VIA Technologies, Inc.
- Rochelle L. Stortz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DETERMINATION OF A HORIZONTAL MINIMUM OF DIGI...
- Publication number 20110095785
- Publication date Apr 28, 2011
- VIA Technologies, Inc.
- Rochelle L. Stortz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROPROCESSOR WITH SUBSTRATE BIAS CLAMPS
- Publication number 20100073073
- Publication date Mar 25, 2010
- VIA Technologies, Inc.
- RAYMOND A. BERTRAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROPROCESSOR WITH SELECTIVE SUBSTRATE BIASING FOR CLOCK-GATED FUN...
- Publication number 20100073074
- Publication date Mar 25, 2010
- VIA Technologies, Inc.
- RAYMOND A. BERTRAM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATA BUS INVERSION DETECTION MECHANISM
- Publication number 20090077286
- Publication date Mar 19, 2009
- VIA TECHNOLOGIES, INC.
- Raymond A. Bertram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATED P-CHANNEL DYNAMIC REGISTER
- Publication number 20080036502
- Publication date Feb 14, 2008
- VIA Technologies, Inc.
- JAMES R. LUNDBERG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ACCELERATED N-CHANNEL DYNAMIC REGISTER
- Publication number 20080036501
- Publication date Feb 14, 2008
- VIA Technologies, Inc.
- JAMES R. LUNDBERG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
P-DOMINO REGISTER WITH ACCELERATED NON-CHARGE PATH
- Publication number 20070290720
- Publication date Dec 20, 2007
- VIA Technologies, Inc.
- IMRAN QURESHI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
N-DOMINO REGISTER WITH ACCELERATED NON-DISCHARGE PATH
- Publication number 20070290719
- Publication date Dec 20, 2007
- VIA Technologies, Inc.
- IMRAN QURESHI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Inverting dynamic register with data-dependent hold time reduction...
- Publication number 20060158226
- Publication date Jul 20, 2006
- VIA Technologies, Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
P-domino register
- Publication number 20060038589
- Publication date Feb 23, 2006
- VIA Technologies, Inc.
- James R. Lundberg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
P-domino output latch
- Publication number 20060038590
- Publication date Feb 23, 2006
- VIA Technologies, Inc.
- James R. Lundberg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
N-domino output latch
- Publication number 20060033534
- Publication date Feb 16, 2006
- VIA TECHNOLOGIES, INC.
- James R. Lundberg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
P-domino output latch with accelerated evaluate path
- Publication number 20050248368
- Publication date Nov 10, 2005
- VIA Technologies, Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Non-inverting domino register
- Publication number 20050127952
- Publication date Jun 16, 2005
- VIA Technologies Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dynamic multi-input priority multiplexer
- Publication number 20050012540
- Publication date Jan 20, 2005
- VIA Technologies Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
N-domino output latch with accelerated evaluate path
- Publication number 20040257115
- Publication date Dec 23, 2004
- VIA Technologies, Inc.
- Raymond A. Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Complementary input dynamic logic for complex logic functions
- Publication number 20040056685
- Publication date Mar 25, 2004
- IP-First LLC
- Mir Azam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Non-inverting domino register
- Publication number 20040034681
- Publication date Feb 19, 2004
- IP-First LLC
- Raymond Bertram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Optimization of clock network capacitance on an integrated circuit
- Publication number 20030233623
- Publication date Dec 18, 2003
- IP-First LLC
- Raymond Bertram
- G06 - COMPUTING CALCULATING COUNTING

Raymond Bertram

Person

Patents Grantslast 30 patents

System and method for determination of a horizontal minimum of digi...

System and method of using common adder circuitry for both a horizo...

Microprocessor with selective substrate biasing for clock-gated fun...

Microprocessor with substrate bias clamps

Data bus inversion detection mechanism

N-domino output latch

Accelerated P-channel dynamic register

Inverting dynamic register with data-dependent hold time reduction...

Accelerated N-channel dynamic register

P-domino register with accelerated non-charge path

N-domino register with accelerated non-discharge path

Non-inverting domino register

P-domino register

P-domino output latch

Non-inverting domino register

Optimization of clock network capacitance on an integrated circuit

Dynamic multi-input priority multiplexer

P-domino output latch with accelerated evaluate path

N-domino output latch with accelerated evaluate path

Complementary input dynamic logic for complex logic functions

Patents Applicationslast 30 patents

SYSTEM AND METHOD OF USING COMMON ADDER CIRCUITRY FOR BOTH A HORIZO...

SYSTEM AND METHOD FOR DETERMINATION OF A HORIZONTAL MINIMUM OF DIGI...

MICROPROCESSOR WITH SUBSTRATE BIAS CLAMPS

MICROPROCESSOR WITH SELECTIVE SUBSTRATE BIASING FOR CLOCK-GATED FUN...

DATA BUS INVERSION DETECTION MECHANISM

ACCELERATED P-CHANNEL DYNAMIC REGISTER

ACCELERATED N-CHANNEL DYNAMIC REGISTER

P-DOMINO REGISTER WITH ACCELERATED NON-CHARGE PATH

N-DOMINO REGISTER WITH ACCELERATED NON-DISCHARGE PATH

Inverting dynamic register with data-dependent hold time reduction...

P-domino register

P-domino output latch

N-domino output latch

P-domino output latch with accelerated evaluate path

Non-inverting domino register

Dynamic multi-input priority multiplexer

N-domino output latch with accelerated evaluate path

Complementary input dynamic logic for complex logic functions

Non-inverting domino register

Optimization of clock network capacitance on an integrated circuit