Raymond C. Pang

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Electronic fuse array
- Patent number 7,710,813
- Issue date May 4, 2010
- Xilinx, Inc.
- Hsung Jai Im
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell with single-event-upset tolerance
- Patent number 7,638,822
- Issue date Dec 29, 2009
- Xilinx, Inc.
- Jan L. de Jong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with fuse programming damage detection
- Patent number 7,598,749
- Issue date Oct 6, 2009
- Xilinx, Inc.
- Boon Yong Ang
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and methods of using parallel counter controlled delay lin...
- Patent number 7,535,278
- Issue date May 19, 2009
- Xilinx, Inc.
- Robert M. Ondris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaved memory cell with single-event-upset tolerance
- Patent number 7,515,452
- Issue date Apr 7, 2009
- Xilinx, Inc.
- Jan L. de Jong
- G11 - INFORMATION STORAGE
Information Patent Grant
eFuse resistance sensing scheme with improved accuracy
- Patent number 7,501,879
- Issue date Mar 10, 2009
- Xilinx, Inc.
- Kwansuhk Oh
- G11 - INFORMATION STORAGE
Information Patent Grant
Yield-enhancing methods of providing a family of scaled integrated...
- Patent number 7,491,576
- Issue date Feb 17, 2009
- Xilinx, Inc.
- Steven P. Young
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scalable columnar boundary scan architecture for integrated circuits
- Patent number 7,451,369
- Issue date Nov 11, 2008
- Xilinx, Inc.
- Kwansuhk Oh
- G01 - MEASURING TESTING
Information Patent Grant
Methods of providing families of integrated circuits with similar d...
- Patent number 7,402,443
- Issue date Jul 22, 2008
- Xilinx, Inc.
- Raymond C. Pang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-product die configurable as two or more programmable integrat...
- Patent number 7,345,507
- Issue date Mar 18, 2008
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for and method of implementing a content addressable memory...
- Patent number 7,248,491
- Issue date Jul 24, 2007
- Xilinx, Inc.
- Alvin Y. Ching
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of transferring data in memory device
- Patent number 7,242,633
- Issue date Jul 10, 2007
- Xilinx, Inc.
- Alvin Y. Ching
- G11 - INFORMATION STORAGE
Information Patent Grant
Trim unit having less jitter
- Patent number 7,190,202
- Issue date Mar 13, 2007
- Xilink, Inc.
- Kwansuhk Oh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital clock manager capacitive trim unit
- Patent number 7,157,951
- Issue date Jan 2, 2007
- Xilinx, Inc.
- Shawn K. Morrison
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with decryption and structure for prevent...
- Patent number 7,117,372
- Issue date Oct 3, 2006
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bitstream for configuring a PLD with encrypted design data
- Patent number 7,117,373
- Issue date Oct 3, 2006
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partially encrypted bitstream method
- Patent number 7,058,177
- Issue date Jun 6, 2006
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase matched clock divider
- Patent number 7,046,052
- Issue date May 16, 2006
- Xilinx, Inc.
- Andrew K. Percey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital clock manager having cascade voltage switch logic clock paths
- Patent number 7,038,519
- Issue date May 2, 2006
- Xilinx, Inc.
- Raymond C. Pang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with method of preventing readback
- Patent number 6,981,153
- Issue date Dec 27, 2005
- Xilinx, Inc.
- Raymond C. Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure and method for loading encryption keys through a test acc...
- Patent number 6,965,675
- Issue date Nov 15, 2005
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encryption key for multi-key encryption in programmable logic device
- Patent number 6,957,340
- Issue date Oct 18, 2005
- Xilinx, Inc.
- Raymond C. Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with decryption algorithm and decryption key
- Patent number 6,931,543
- Issue date Aug 16, 2005
- Xilinx, Inc.
- Raymond C. Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration enable bits for PLD configurable blocks
- Patent number 6,897,676
- Issue date May 24, 2005
- Xilinx, Inc.
- Raymond C. Pang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay line trim unit having consistent performance under varying pr...
- Patent number 6,664,837
- Issue date Dec 16, 2003
- Xilinx, Inc.
- Kwansuhk Oh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with partial battery backup
- Patent number 6,441,641
- Issue date Aug 27, 2002
- Xilinx, Inc.
- Raymond C. Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block RAM having multiple configurable write modes for use in a fie...
- Patent number 6,373,779
- Issue date Apr 16, 2002
- Xilinx, Inc.
- Raymond C. Pang
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile/battery-backed key in PLD
- Patent number 6,366,117
- Issue date Apr 2, 2002
- Xilinx, Inc.
- Raymond C. Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardwire logic device emulating any of two or more FPGAs
- Patent number 6,353,921
- Issue date Mar 5, 2002
- Xilinx, Inc.
- Edwin S. Law
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block RAM with configurable data width and parity for use in a fiel...
- Patent number 6,346,825
- Issue date Feb 12, 2002
- Xilinx, Inc.
- Raymond C. Pang
- H03 - BASIC ELECTRONIC CIRCUITRY

Raymond C. Pang

Person

Patents Grantslast 30 patents

Electronic fuse array

Memory cell with single-event-upset tolerance

Integrated circuit with fuse programming damage detection

Circuits and methods of using parallel counter controlled delay lin...

Interleaved memory cell with single-event-upset tolerance

eFuse resistance sensing scheme with improved accuracy

Yield-enhancing methods of providing a family of scaled integrated...

Scalable columnar boundary scan architecture for integrated circuits

Methods of providing families of integrated circuits with similar d...

Multi-product die configurable as two or more programmable integrat...

Circuit for and method of implementing a content addressable memory...

Memory device and method of transferring data in memory device

Trim unit having less jitter

Digital clock manager capacitive trim unit

Programmable logic device with decryption and structure for prevent...

Bitstream for configuring a PLD with encrypted design data

Partially encrypted bitstream method

Phase matched clock divider

Digital clock manager having cascade voltage switch logic clock paths

Programmable logic device with method of preventing readback

Structure and method for loading encryption keys through a test acc...

Encryption key for multi-key encryption in programmable logic device

Programmable logic device with decryption algorithm and decryption key

Configuration enable bits for PLD configurable blocks

Delay line trim unit having consistent performance under varying pr...

Programmable logic device with partial battery backup

Block RAM having multiple configurable write modes for use in a fie...

Nonvolatile/battery-backed key in PLD

Hardwire logic device emulating any of two or more FPGAs

Block RAM with configurable data width and parity for use in a fiel...