Raymond X. Nijssen

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cascade communications between FPGA tiles
- Patent number 12,141,088
- Issue date Nov 12, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused memory and arithmetic circuit
- Patent number 12,034,446
- Issue date Jul 9, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple mode arithmetic circuit
- Patent number 12,014,150
- Issue date Jun 18, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascade communications between FPGA tiles
- Patent number 11,734,216
- Issue date Aug 22, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple mode arithmetic circuit
- Patent number 11,650,792
- Issue date May 16, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascade communications between FPGA tiles
- Patent number 11,288,220
- Issue date Mar 29, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple mode arithmetic circuit
- Patent number 11,256,476
- Issue date Feb 22, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient FPGA multipliers
- Patent number 10,963,221
- Issue date Mar 30, 2021
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused memory and arithmetic circuit
- Patent number 10,790,830
- Issue date Sep 29, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient FPGA multipliers
- Patent number 10,656,915
- Issue date May 19, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asychronous system analysis
- Patent number 8,661,378
- Issue date Feb 25, 2014
- Achronix Semiconductor Corporation
- Rajit Manohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
One phase logic
- Patent number 8,593,176
- Issue date Nov 26, 2013
- Achronix Semiconductor Corporation
- Raymond Nijssen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-clock asynchronous logic circuits
- Patent number 8,301,933
- Issue date Oct 30, 2012
- Achronix Semiconductor Corporation
- Rajit Manohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Token enhanced asynchronous conversion of synchonous circuits
- Patent number 8,234,607
- Issue date Jul 31, 2012
- Achronix Semiconductor Corporation
- Virantha Ekanayake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
One phase logic
- Patent number 8,106,683
- Issue date Jan 31, 2012
- Achronix Semiconductor Corporation
- Raymond Nijssen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Asynchronous conversion circuitry apparatus, systems, and methods
- Patent number 8,078,899
- Issue date Dec 13, 2011
- Achronix Semiconductor Corporation
- Rajit Manohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous circuit representation of synchronous circuit with asy...
- Patent number 7,982,502
- Issue date Jul 19, 2011
- Achronix Semiconductor Corporation
- Rajit Manohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
One phase logic
- Patent number 7,932,746
- Issue date Apr 26, 2011
- Achronix Semiconductor Corporation
- Raymond Nijssen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Asynchronous conversion circuitry apparatus, systems, and methods
- Patent number 7,900,078
- Issue date Mar 1, 2011
- Achronix Semiconductor Corporation
- Rajit Manohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Subgrid detailed routing
- Patent number 6,507,941
- Issue date Jan 14, 2003
- Magma Design Automation, Inc.
- Hardy Kwok-Shing Leung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated design of parallel drive standard cells
- Patent number 6,496,965
- Issue date Dec 17, 2002
- Magma Design Automation, Inc.
- Lukas P. P. P. van Ginneken
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20240248682
- Publication date Jul 25, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED MEMORY AND ARITHMETIC CIRCUIT
- Publication number 20240235556
- Publication date Jul 11, 2024
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONFLICT-FREE PARALLEL RADIX SORTING DEVICE, SYSTEM AND METHOD
- Publication number 20230409201
- Publication date Dec 21, 2023
- Anchronix Semiconductor Corporation
- Marcel Van der Goot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CASCADE COMMUNICATIONS BETWEEN FPGA TILES
- Publication number 20230325334
- Publication date Oct 12, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20230244446
- Publication date Aug 3, 2023
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CASCADE COMMUNICATIONS BETWEEN FPGA TILES
- Publication number 20220214990
- Publication date Jul 7, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20220129244
- Publication date Apr 28, 2022
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CASCADE COMMUNICATIONS BETWEEN FPGA TILES
- Publication number 20210117356
- Publication date Apr 22, 2021
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Mode Arithmetic Circuit
- Publication number 20210042087
- Publication date Feb 11, 2021
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED MEMORY AND ARITHMETIC CIRCUIT
- Publication number 20200373925
- Publication date Nov 26, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EFFICIENT FPGA MULTIPLIERS
- Publication number 20200195951
- Publication date Jun 18, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EFFICIENT FPGA MULTIPLIERS
- Publication number 20200019375
- Publication date Jan 16, 2020
- Achronix Semiconductor Corporation
- Daniel Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ONE PHASE LOGIC
- Publication number 20120112792
- Publication date May 10, 2012
- Raymond Nijssen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ONE PHASE LOGIC
- Publication number 20110298495
- Publication date Dec 8, 2011
- ACHRONIX SEMICONDUCTOR CORPORATION
- Raymond Nijssen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS
- Publication number 20110130171
- Publication date Jun 2, 2011
- ACHRONIX SEMICONDUCTOR CORPORATION
- Rajit Manohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYCHRONOUS SYSTEM ANALYSIS
- Publication number 20110078644
- Publication date Mar 31, 2011
- Rajit Manohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS
- Publication number 20110062987
- Publication date Mar 17, 2011
- Rajit Manohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOKEN ENHANCED ASYNCHRONOUS CONVERSION OF SYNCHONOUS CIRCUITS
- Publication number 20110066986
- Publication date Mar 17, 2011
- Virantha Ekanayake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CLOCK ASYNCHRONOUS LOGIC CIRCUITS
- Publication number 20110066873
- Publication date Mar 17, 2011
- Rajit Manohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS CIRCUIT REPRESENTATION OF SYNCHRONOUS CIRCUIT WITH ASY...
- Publication number 20110062991
- Publication date Mar 17, 2011
- Rajit Manohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Subgrid detailed routing
- Publication number 20030121018
- Publication date Jun 26, 2003
- Hardy Kwok-Shing Leung
- G06 - COMPUTING CALCULATING COUNTING

Raymond X. Nijssen

Person

Patents Grantslast 30 patents

Cascade communications between FPGA tiles

Fused memory and arithmetic circuit

Multiple mode arithmetic circuit

Cascade communications between FPGA tiles

Multiple mode arithmetic circuit

Cascade communications between FPGA tiles

Multiple mode arithmetic circuit

Efficient FPGA multipliers

Fused memory and arithmetic circuit

Efficient FPGA multipliers

Asychronous system analysis

One phase logic

Multi-clock asynchronous logic circuits

Token enhanced asynchronous conversion of synchonous circuits

One phase logic

Asynchronous conversion circuitry apparatus, systems, and methods

Asynchronous circuit representation of synchronous circuit with asy...

One phase logic

Asynchronous conversion circuitry apparatus, systems, and methods

Subgrid detailed routing

Automated design of parallel drive standard cells

Patents Applicationslast 30 patents

Multiple Mode Arithmetic Circuit

FUSED MEMORY AND ARITHMETIC CIRCUIT

CONFLICT-FREE PARALLEL RADIX SORTING DEVICE, SYSTEM AND METHOD

CASCADE COMMUNICATIONS BETWEEN FPGA TILES

Multiple Mode Arithmetic Circuit

CASCADE COMMUNICATIONS BETWEEN FPGA TILES

Multiple Mode Arithmetic Circuit

CASCADE COMMUNICATIONS BETWEEN FPGA TILES

Multiple Mode Arithmetic Circuit

FUSED MEMORY AND ARITHMETIC CIRCUIT

EFFICIENT FPGA MULTIPLIERS

EFFICIENT FPGA MULTIPLIERS

ONE PHASE LOGIC

ONE PHASE LOGIC

ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS

ASYCHRONOUS SYSTEM ANALYSIS

ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS

TOKEN ENHANCED ASYNCHRONOUS CONVERSION OF SYNCHONOUS CIRCUITS

MULTI-CLOCK ASYNCHRONOUS LOGIC CIRCUITS

ASYNCHRONOUS CIRCUIT REPRESENTATION OF SYNCHRONOUS CIRCUIT WITH ASY...

Subgrid detailed routing