Razak Hossain

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Frequency doubler with duty cycle correction
- Patent number 11,595,028
- Issue date Feb 28, 2023
- QUALCOMM Incorporated
- Masoud Moslehi Bajestan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Calibration of sampling-based multiplying delay-locked loop (MDLL)
- Patent number 11,411,569
- Issue date Aug 9, 2022
- QUALCOMM Incorporated
- Masoud Moslehi Bajestan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan chain modification for reduced leakage
- Patent number 9,032,354
- Issue date May 12, 2015
- STMicroelectronics, Inc.
- Razak Hossain
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain modification for reduced leakage
- Patent number 8,453,098
- Issue date May 28, 2013
- STMicroelectronics, Inc.
- Razak Hossain
- G01 - MEASURING TESTING
Information Patent Grant
Parallel mash ΔΣ modulator
- Patent number 8,203,475
- Issue date Jun 19, 2012
- ST-Ericsson SA
- Razak Hossain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan chain modification for reduced leakage
- Patent number 7,571,402
- Issue date Aug 4, 2009
- STMicroelectronics, Inc.
- Razak Hossain
- G01 - MEASURING TESTING
Information Patent Grant
Crosstalk noise reduction circuit and method
- Patent number 7,337,419
- Issue date Feb 26, 2008
- STMicroelectronics, Inc.
- Razak Hossain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Domino logic compatible scannable flip-flop
- Patent number 7,301,372
- Issue date Nov 27, 2007
- STMicroelectronics, Inc.
- Scott B. Anderson
- G01 - MEASURING TESTING
Information Patent Grant
Method for synthesizing domino logic circuits cross reference to re...
- Patent number 7,254,796
- Issue date Aug 7, 2007
- STMicroelectronics, Inc.
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Domino logic compatible scannable flip-flop
- Patent number 7,002,374
- Issue date Feb 21, 2006
- STMicroelectronics, Inc.
- Scott B. Anderson
- G01 - MEASURING TESTING
Information Patent Grant
Method for synthesizing domino logic circuits
- Patent number 6,954,909
- Issue date Oct 11, 2005
- STMicroelectronics, Inc.
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulse triggered static flip-flop having scan test
- Patent number 6,911,845
- Issue date Jun 28, 2005
- STMicroelectronics, Inc.
- Razak Hossain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for predictive comparator following addition
- Patent number 6,820,109
- Issue date Nov 16, 2004
- STMicroelectronics, Inc.
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for determining the number of logical one values on a data bus
- Patent number 6,729,168
- Issue date May 4, 2004
- STMicroelectronics, Inc.
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for detecting numbers equal to a power of two on a data bus
- Patent number 6,665,691
- Issue date Dec 16, 2003
- STMicroelectronics, Inc.
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PHASE TRACKING AND CORRECTION ARCHITECTURE
- Publication number 20240106623
- Publication date Mar 28, 2024
- QUALCOMM Incorporated
- Gang LIU
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS
- Publication number 20240097689
- Publication date Mar 21, 2024
- QUALCOMM Incorporated
- Jianjun YU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Frequency Doubler with Duty Cycle Correction
- Publication number 20210409007
- Publication date Dec 30, 2021
- QUALCOMM Incorporated
- Masoud Moslehi Bajestan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Calibration of Sampling-Based Multiplying Delay-Locked Loop (MDLL)
- Publication number 20210409029
- Publication date Dec 30, 2021
- QUALCOMM Incorporated
- Masoud Moslehi Bajestan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
WIDE TUNING RANGE OSCILLATOR
- Publication number 20200177126
- Publication date Jun 4, 2020
- QUALCOMM Incorporated
- Gang LIU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN CHAIN MODIFICATION FOR REDUCED LEAKAGE
- Publication number 20130262944
- Publication date Oct 3, 2013
- STMicroelectronics, Inc.
- Razak Hossain
- G01 - MEASURING TESTING
Information Patent Application
PARALLEL MASH DELTA SIGMA MODULATOR
- Publication number 20110285565
- Publication date Nov 24, 2011
- ST-ERICSSON SA
- Razak Hossain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Scan chain modification for reduced leakage
- Publication number 20090193307
- Publication date Jul 30, 2009
- Razak Hossain
- G01 - MEASURING TESTING
Information Patent Application
Crosstalk Noise Reduction Circuit and Method
- Publication number 20080100367
- Publication date May 1, 2008
- STMicroelectronics, Inc.
- Razak Hossain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Domino logic compatible scannable flip-flop
- Publication number 20060114029
- Publication date Jun 1, 2006
- Scott B. Anderson
- G01 - MEASURING TESTING
Information Patent Application
Crosstalk noise reduction circuit and method
- Publication number 20060039551
- Publication date Feb 23, 2006
- Razak Hossain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for synthesizing domino logic circuits
- Publication number 20050278681
- Publication date Dec 15, 2005
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN CHAIN MODIFICATION FOR REDUCED LEAKAGE
- Publication number 20050050416
- Publication date Mar 3, 2005
- STMICROELECTRONICS, INC,
- Razak Hossain
- G01 - MEASURING TESTING
Information Patent Application
PULSE TRIGGERED STATIC FLIP-FLOP HAVING SCAN TEST
- Publication number 20040196067
- Publication date Oct 7, 2004
- STMicroelectronics, Inc.
- Razak Hossain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DOMINO LOGIC COMPATIBLE SCANNABLE FLIP-FLOP
- Publication number 20040155678
- Publication date Aug 12, 2004
- Scott B. Anderson
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR SYNTHESIZING DOMINO LOGIC CIRCUITS
- Publication number 20040158807
- Publication date Aug 12, 2004
- STMicroelectronics, Inc.
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for predictive comparator following addition
- Publication number 20030050951
- Publication date Mar 13, 2003
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit for detecting numbers equal to a power of two on a data bus
- Publication number 20020111976
- Publication date Aug 15, 2002
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit for determining the number of logical one values on a data bus
- Publication number 20020073127
- Publication date Jun 13, 2002
- Razak Hossain
- G06 - COMPUTING CALCULATING COUNTING

Razak Hossain

Person

Patents Grantslast 30 patents

Frequency doubler with duty cycle correction

Calibration of sampling-based multiplying delay-locked loop (MDLL)

Scan chain modification for reduced leakage

Scan chain modification for reduced leakage

Parallel mash ΔΣ modulator

Scan chain modification for reduced leakage

Crosstalk noise reduction circuit and method

Domino logic compatible scannable flip-flop

Method for synthesizing domino logic circuits cross reference to re...

Domino logic compatible scannable flip-flop

Method for synthesizing domino logic circuits

Pulse triggered static flip-flop having scan test

System and method for predictive comparator following addition

Circuit for determining the number of logical one values on a data bus

Circuit for detecting numbers equal to a power of two on a data bus

Patents Applicationslast 30 patents

PHASE TRACKING AND CORRECTION ARCHITECTURE

SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS

Frequency Doubler with Duty Cycle Correction

Calibration of Sampling-Based Multiplying Delay-Locked Loop (MDLL)

WIDE TUNING RANGE OSCILLATOR

SCAN CHAIN MODIFICATION FOR REDUCED LEAKAGE

PARALLEL MASH DELTA SIGMA MODULATOR

Scan chain modification for reduced leakage

Crosstalk Noise Reduction Circuit and Method

Domino logic compatible scannable flip-flop

Crosstalk noise reduction circuit and method

Method for synthesizing domino logic circuits

SCAN CHAIN MODIFICATION FOR REDUCED LEAKAGE

PULSE TRIGGERED STATIC FLIP-FLOP HAVING SCAN TEST

DOMINO LOGIC COMPATIBLE SCANNABLE FLIP-FLOP

METHOD FOR SYNTHESIZING DOMINO LOGIC CIRCUITS

System and method for predictive comparator following addition

Circuit for detecting numbers equal to a power of two on a data bus

Circuit for determining the number of logical one values on a data bus