Rebecca A. Jessep

Person

Dallas, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Via shielding for power/ground layers on printed circuit board
- Patent number 7,271,349
- Issue date Sep 18, 2007
- Intel Corporation
- Rebecca A. Jessep
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods for forming via shielding
- Patent number 7,168,164
- Issue date Jan 30, 2007
- Intel Corporation
- Rebecca A. Jessep
- G01 - MEASURING TESTING
Information Patent Grant
Arrangement of vias in a substrate to support a ball grid array
- Patent number 7,061,116
- Issue date Jun 13, 2006
- Intel Corporation
- Carolyn McCormick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Printed circuit board conductor channeling
- Patent number 7,061,095
- Issue date Jun 13, 2006
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Standoff devices and methods of using same
- Patent number 6,941,537
- Issue date Sep 6, 2005
- Intel Corporation
- Rebecca A. Jessep
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Coupon registration mechanism and method
- Patent number 6,667,090
- Issue date Dec 23, 2003
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Vented vias for via in pad technology yield improvements
- Patent number 6,580,174
- Issue date Jun 17, 2003
- Intel Corporation
- Carolyn R. McCormick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
Via shielding for power/ground layers on printed circuit board
- Publication number 20040238216
- Publication date Dec 2, 2004
- Rebecca A. Jessep
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Standoff arrangements to control distance and provide electrical fu...
- Publication number 20030145460
- Publication date Aug 7, 2003
- Rebecca A. Jessep
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Via shielding for power/ground layers on printed circuit board
- Publication number 20030091730
- Publication date May 15, 2003
- Rebecca A. Jessep
- G01 - MEASURING TESTING
Information Patent Application
VENTED VIAS FOR VIA IN PAD TECHNOLOGY YIELD IMPROVEMENTS
- Publication number 20030064546
- Publication date Apr 3, 2003
- Carolyn R. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and method for printed circuit board conductor channeling
- Publication number 20030061590
- Publication date Mar 27, 2003
- David W. Boggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Arrangement of vias in a substrate to support a ball grid array
- Publication number 20030057974
- Publication date Mar 27, 2003
- Carolyn McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Coupon registration mechanism and method
- Publication number 20030056365
- Publication date Mar 27, 2003
- David W. Boggs
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
Grid array mounting arrangements
- Publication number 20030047348
- Publication date Mar 13, 2003
- Rebecca Jessep
- H01 - BASIC ELECTRIC ELEMENTS

Rebecca A. Jessep

Person

Patents Grantslast 30 patents

Via shielding for power/ground layers on printed circuit board

Methods for forming via shielding

Arrangement of vias in a substrate to support a ball grid array

Printed circuit board conductor channeling

Standoff devices and methods of using same

Coupon registration mechanism and method

Vented vias for via in pad technology yield improvements

Patents Applicationslast 30 patents

Via shielding for power/ground layers on printed circuit board

Standoff arrangements to control distance and provide electrical fu...

Via shielding for power/ground layers on printed circuit board

VENTED VIAS FOR VIA IN PAD TECHNOLOGY YIELD IMPROVEMENTS

System and method for printed circuit board conductor channeling

Arrangement of vias in a substrate to support a ball grid array

Coupon registration mechanism and method

Grid array mounting arrangements