Reid James Riedlinger

Person

Wellington, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Managing power consumption in a multi-core processor
- Patent number 9,075,614
- Issue date Jul 7, 2015
- Intel Corporation
- Eric Fetzer
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method for preventing processor errors
- Patent number 8,423,832
- Issue date Apr 16, 2013
- Hewlett-Packard Development Company, L.P.
- Reid J. Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for adjusting operating points of a processor bas...
- Patent number 8,020,038
- Issue date Sep 13, 2011
- Hewlett-Packard Development Company, L.P.
- Reid J. Riedlinger
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Circuit and circuit design method
- Patent number 7,698,673
- Issue date Apr 13, 2010
- Hewlett-Packard Development Company, L.P.
- Steven Ray Afleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for testing a processor
- Patent number 7,590,509
- Issue date Sep 15, 2009
- Hewlett-Packard Development Company, L.P.
- Reid J. Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Content addressable memory selectively addressable in a physical ad...
- Patent number 7,146,457
- Issue date Dec 5, 2006
- Hewlett-Packard Development Company, L.P.
- Kuldeep Simha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-ported read SRAM cell with improved soft error immunity
- Patent number 6,873,565
- Issue date Mar 29, 2005
- Hewlett-Packard Development Company, L.P.
- Reid James Riedlinger
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method utilizing speculative cache access for improved p...
- Patent number 6,647,464
- Issue date Nov 11, 2003
- Hewlett-Packard Development Company, L.P.
- Reid James Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latching annihilation based logic gate
- Patent number 6,583,650
- Issue date Jun 24, 2003
- Hewlett-Packard Development Company
- Samuel D Naffziger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cache chain structure to implement high bandwidth low latency cache...
- Patent number 6,557,078
- Issue date Apr 29, 2003
- Hewlett-Packard Development Company, L.P.
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self test for content addressable memory
- Patent number 6,550,034
- Issue date Apr 15, 2003
- Hewlett-Packard Development Company, L.P.
- Reid James Riedlinger
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for TLB buddy entry self-timing
- Patent number 6,539,466
- Issue date Mar 25, 2003
- Hewlett-Packard Company
- Reid James Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache address conflict mechanism without store buffers
- Patent number 6,539,457
- Issue date Mar 25, 2003
- Hewlett-Packard Company
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L1 cache memory
- Patent number 6,507,892
- Issue date Jan 14, 2003
- Hewlett-Packard Company
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latching annihilation based logic gate
- Patent number 6,459,304
- Issue date Oct 1, 2002
- Hewlett-Packard Company
- Samuel D Naffziger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Virtual address bypassing using local page mask
- Patent number 6,446,187
- Issue date Sep 3, 2002
- Hewlett-Packard Company
- Reid James Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple issue algorithm with over subscription avoidance feature t...
- Patent number 6,427,189
- Issue date Jul 30, 2002
- Hewlett-Packard Company
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for enabling/disabling SRAM banks for memory access
- Patent number 6,285,579
- Issue date Sep 4, 2001
- Hewlett-Packard Company
- Reid James Riedlinger
- G11 - INFORMATION STORAGE
Information Patent Grant
Register structure with a dual-ended write mechanism
- Patent number 6,226,217
- Issue date May 1, 2001
- Hewlett-Packard Company
- Reid James Riedlinger
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-ported register structure utilizing a pulse write mechanism
- Patent number 6,208,565
- Issue date Mar 27, 2001
- Hewlett-Packard Company
- Reid James Riedlinger
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated weak write test mode (WWWTM)
- Patent number 6,192,001
- Issue date Feb 20, 2001
- Hewlett-Packard Company
- Donald R Weiss
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR
- Publication number 20130232368
- Publication date Sep 5, 2013
- ERIC FETZER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for adjusting operating points of a processor bas...
- Publication number 20080155321
- Publication date Jun 26, 2008
- Reid J. Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for preventing processor errors
- Publication number 20080126826
- Publication date May 29, 2008
- Reid J. Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for testing a processor
- Publication number 20060290365
- Publication date Dec 28, 2006
- Reid J. Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit and circuit design method
- Publication number 20060055428
- Publication date Mar 16, 2006
- Steven Ray Affleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-PORTED READ SRAM CELL WITH IMPROVED SOFT ERROR IMMUNITY
- Publication number 20050078543
- Publication date Apr 14, 2005
- Reid James Riedlinger
- G11 - INFORMATION STORAGE
Information Patent Application
Content addressable memory
- Publication number 20050066115
- Publication date Mar 24, 2005
- Kuldeep Simha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for and method of unlimited voltage multi ported sram cells
- Publication number 20040053510
- Publication date Mar 18, 2004
- Casey J. Little
- G11 - INFORMATION STORAGE
Information Patent Application
Bank conflict determination
- Publication number 20030163643
- Publication date Aug 28, 2003
- Reid James Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method utilizing speculative cache access for improved p...
- Publication number 20020169929
- Publication date Nov 14, 2002
- Reid James Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latching annihilation based logic gate
- Publication number 20020030512
- Publication date Mar 14, 2002
- Samuel D. Naffziger
- H03 - BASIC ELECTRONIC CIRCUITRY

Reid James Riedlinger

Person

Patents Grantslast 30 patents

Managing power consumption in a multi-core processor

System and method for preventing processor errors

System and method for adjusting operating points of a processor bas...

Circuit and circuit design method

System and method for testing a processor

Content addressable memory selectively addressable in a physical ad...

Dual-ported read SRAM cell with improved soft error immunity

System and method utilizing speculative cache access for improved p...

Latching annihilation based logic gate

Cache chain structure to implement high bandwidth low latency cache...

Built-in self test for content addressable memory

System and method for TLB buddy entry self-timing

Cache address conflict mechanism without store buffers

L1 cache memory

Latching annihilation based logic gate

Virtual address bypassing using local page mask

Multiple issue algorithm with over subscription avoidance feature t...

System and method for enabling/disabling SRAM banks for memory access

Register structure with a dual-ended write mechanism

Multi-ported register structure utilizing a pulse write mechanism

Integrated weak write test mode (WWWTM)

Patents Applicationslast 30 patents

MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR

System and method for adjusting operating points of a processor bas...

System and method for preventing processor errors

System and method for testing a processor

Circuit and circuit design method

DUAL-PORTED READ SRAM CELL WITH IMPROVED SOFT ERROR IMMUNITY

Content addressable memory

System for and method of unlimited voltage multi ported sram cells

Bank conflict determination

System and method utilizing speculative cache access for improved p...

Latching annihilation based logic gate