Rejitha Nair

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System on a chip with an integrated configurable safety master micr...
- Patent number 12,271,289
- Issue date Apr 8, 2025
- Texas Instruments Incorporated
- Venkateswar Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed mechanism for fine-grained test power control
- Patent number 12,217,102
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with state machine for pre-boot self-tests
- Patent number 12,158,836
- Issue date Dec 3, 2024
- Texas Instruments Incorporated
- Venkateswar Reddy Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with low power mode management
- Patent number 12,132,386
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Venkateswar Kowkutla
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Technique for clock alignment supporting reset isolation
- Patent number 12,072,731
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Varun Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System on a chip with an integrated configurable safety master micr...
- Patent number 11,899,563
- Issue date Feb 13, 2024
- Texas Instruments Incorporated
- Venkateswar Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with state machine for pre-boot self-tests
- Patent number 11,663,111
- Issue date May 30, 2023
- Texas Instruments Incorporated
- Venkateswar Reddy Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for clock alignment supporting reset isolation
- Patent number 11,662,763
- Issue date May 30, 2023
- Texas Instruments Incorporated
- Varun Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware implementation of a Galois field multiplier
- Patent number 8,650,239
- Issue date Feb 11, 2014
- Texas Instruments Incorporated
- Shriram D. Moharil
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICR...
- Publication number 20250199941
- Publication date Jun 19, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED MECHANISM FOR FINE-GRAINED TEST POWER CONTROL
- Publication number 20250123903
- Publication date Apr 17, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan VARADARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICR...
- Publication number 20240134776
- Publication date Apr 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR CLOCK ALIGNMENT SUPPORTING RESET ISOLATION
- Publication number 20230280784
- Publication date Sep 7, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Varun SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH STATE MACHINE FOR PRE-BOOT SELF-TESTS
- Publication number 20230259448
- Publication date Aug 17, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Reddy KOWKUTLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH LOW POWER MODE MANAGEMENT
- Publication number 20230238872
- Publication date Jul 27, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Kowkutla
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
POWER-ON-RESET SIGNAL ISOLATION DURING LOWER POWER MODE
- Publication number 20230205305
- Publication date Jun 29, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICR...
- Publication number 20230205672
- Publication date Jun 29, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED MECHANISM FOR FINE-GRAINED TEST POWER CONTROL
- Publication number 20230185633
- Publication date Jun 15, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan VARADARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR CLOCK ALIGNMENT SUPPORTING RESET ISOLATION
- Publication number 20230168709
- Publication date Jun 1, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Varun SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH STATE MACHINE FOR PRE-BOOT SELF-TESTS
- Publication number 20210209003
- Publication date Jul 8, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Reddy KOWKUTLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware Implementation of a Galois Field Multiplier
- Publication number 20110060782
- Publication date Mar 10, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Shriram D. Moharil
- G06 - COMPUTING CALCULATING COUNTING

Rejitha Nair

Person

Patents Grantslast 30 patents

System on a chip with an integrated configurable safety master micr...

Distributed mechanism for fine-grained test power control

Integrated circuit with state machine for pre-boot self-tests

Integrated circuit with low power mode management

Technique for clock alignment supporting reset isolation

System on a chip with an integrated configurable safety master micr...

Integrated circuit with state machine for pre-boot self-tests

Technique for clock alignment supporting reset isolation

Hardware implementation of a Galois field multiplier

Patents Applicationslast 30 patents

SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICR...

DISTRIBUTED MECHANISM FOR FINE-GRAINED TEST POWER CONTROL

SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICR...

TECHNIQUE FOR CLOCK ALIGNMENT SUPPORTING RESET ISOLATION

INTEGRATED CIRCUIT WITH STATE MACHINE FOR PRE-BOOT SELF-TESTS

INTEGRATED CIRCUIT WITH LOW POWER MODE MANAGEMENT

POWER-ON-RESET SIGNAL ISOLATION DURING LOWER POWER MODE

SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICR...

DISTRIBUTED MECHANISM FOR FINE-GRAINED TEST POWER CONTROL

TECHNIQUE FOR CLOCK ALIGNMENT SUPPORTING RESET ISOLATION

INTEGRATED CIRCUIT WITH STATE MACHINE FOR PRE-BOOT SELF-TESTS

Hardware Implementation of a Galois Field Multiplier