Remy Berthelon

Person

Saint Martin Heres, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Electronic chip with two phase change memories
- Patent number 12,167,703
- Issue date Dec 10, 2024
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
Information Patent Grant
Strained transistors and phase change memory
- Patent number 12,144,187
- Issue date Nov 12, 2024
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
Information Patent Grant
Phase-change memory with an insulating layer on a cavity sidewall
- Patent number 11,800,821
- Issue date Oct 24, 2023
- STMicroelectronics (Crolles 2) SAS
- Philippe Boivin
Information Patent Grant
Strained transistors and phase change memory
- Patent number 11,723,220
- Issue date Aug 8, 2023
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
Information Patent Grant
Electronic chip with two phase change memories
- Patent number 11,690,303
- Issue date Jun 27, 2023
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
Information Patent Grant
Phase-change memory with insulated walls
- Patent number 11,411,177
- Issue date Aug 9, 2022
- STMicroelectronics (Crolles 2) SAS
- Philippe Boivin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit chip with strained NMOS and PMOS transistors
- Patent number 10,777,680
- Issue date Sep 15, 2020
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D SRAM circuit with double gate transistors with improved layout
- Patent number 10,741,565
- Issue date Aug 11, 2020
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized double-gate transistors and fabricating process
- Patent number 10,546,929
- Issue date Jan 28, 2020
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- François Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit comprising balanced cells at the active
- Patent number 10,504,897
- Issue date Dec 10, 2019
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit including balanced cells limiting an active area
- Patent number 10,446,548
- Issue date Oct 15, 2019
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit chip with strained NMOS and PMOS transistors
- Patent number 10,418,486
- Issue date Sep 17, 2019
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming strained MOS transistors
- Patent number 10,263,110
- Issue date Apr 16, 2019
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FABRICATING AN ELECTRONIC CHIP INCLUDING A MEMORY CIRCUIT
- Publication number 20240147737
- Publication date May 2, 2024
- STMicroelectronics (Crolles 2) SAS
- Olivier WEBER
Information Patent Application
ELECTRONIC DEVICE MANUFACTURING METHOD
- Publication number 20230411450
- Publication date Dec 21, 2023
- STMicroelectronics (Crolles 2) SAS
- Remy BERTHELON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED TRANSISTORS AND PHASE CHANGE MEMORY
- Publication number 20230329008
- Publication date Oct 12, 2023
- STMicroelectronics (Crolles 2) SAS
- Remy BERTHELON
Information Patent Application
ELECTRONIC CHIP WITH TWO PHASE CHANGE MEMORIES
- Publication number 20230309423
- Publication date Sep 28, 2023
- STMicroelectronics (Crolles 2) SAS
- Remy BERTHELON
Information Patent Application
PHASE-CHANGE MEMORY
- Publication number 20220336736
- Publication date Oct 20, 2022
- STMicroelectronics (Crolles 2) SAS
- Philippe BOIVIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED TRANSISTORS AND PHASE CHANGE MEMORY
- Publication number 20210343788
- Publication date Nov 4, 2021
- STMicroelectronics (Crolles 2) SAS
- Remy BERTHELON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC CHIP WITH TWO PHASE CHANGE MEMORIES
- Publication number 20210305502
- Publication date Sep 30, 2021
- STMicroelectronics (Crolles 2) SAS
- Remy BERTHELON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHASE-CHANGE MEMORY
- Publication number 20200381617
- Publication date Dec 3, 2020
- STMicroelectronics (Crolles 2) SAS
- Philippe BOIVIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT CHIP WITH STRAINED NMOS AND PMOS TRANSISTORS
- Publication number 20190363190
- Publication date Nov 28, 2019
- STMicroelectronics (Crolles 2) SAS
- Remy BERTHELON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D SRAM CIRCUIT WITH DOUBLE GATE TRANSISTORS WITH IMPROVED LAYOUT
- Publication number 20190312039
- Publication date Oct 10, 2019
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Francois Andrieu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTORS DOUBLE GRILLES OPTIMISES ET PROCEDE DE FABRICATION
- Publication number 20190027560
- Publication date Jan 24, 2019
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- François ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT CHIP WITH STRAINED NMOS AND PMOS TRANSISTORS
- Publication number 20180331221
- Publication date Nov 15, 2018
- STMicroelectronics (Crolles 2) SAS
- Remy BERTHELON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT INCLUDING BALANCED CELLS LIMITING AN ACTIVE AREA
- Publication number 20180083005
- Publication date Mar 22, 2018
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Francois ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT INCLUDING BALANCED CELLS LIMITING AN ACTIVE AREA
- Publication number 20180083006
- Publication date Mar 22, 2018
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Francois ANDRIEU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING STRAINED MOS TRANSISTORS
- Publication number 20170194498
- Publication date Jul 6, 2017
- STMicroelectronics (Crolles 2) SAS
- Remy Berthelon
- H01 - BASIC ELECTRIC ELEMENTS

Remy Berthelon

Person

Patents Grantslast 30 patents

Electronic chip with two phase change memories

Strained transistors and phase change memory

Phase-change memory with an insulating layer on a cavity sidewall

Strained transistors and phase change memory

Electronic chip with two phase change memories

Phase-change memory with insulated walls

Integrated circuit chip with strained NMOS and PMOS transistors

3D SRAM circuit with double gate transistors with improved layout

Optimized double-gate transistors and fabricating process

Integrated circuit comprising balanced cells at the active

Integrated circuit including balanced cells limiting an active area

Integrated circuit chip with strained NMOS and PMOS transistors

Method of forming strained MOS transistors

Patents Applicationslast 30 patents

METHOD OF FABRICATING AN ELECTRONIC CHIP INCLUDING A MEMORY CIRCUIT

ELECTRONIC DEVICE MANUFACTURING METHOD

STRAINED TRANSISTORS AND PHASE CHANGE MEMORY

ELECTRONIC CHIP WITH TWO PHASE CHANGE MEMORIES

PHASE-CHANGE MEMORY

STRAINED TRANSISTORS AND PHASE CHANGE MEMORY

ELECTRONIC CHIP WITH TWO PHASE CHANGE MEMORIES

PHASE-CHANGE MEMORY

INTEGRATED CIRCUIT CHIP WITH STRAINED NMOS AND PMOS TRANSISTORS

3D SRAM CIRCUIT WITH DOUBLE GATE TRANSISTORS WITH IMPROVED LAYOUT

TRANSISTORS DOUBLE GRILLES OPTIMISES ET PROCEDE DE FABRICATION

INTEGRATED CIRCUIT CHIP WITH STRAINED NMOS AND PMOS TRANSISTORS

INTEGRATED CIRCUIT INCLUDING BALANCED CELLS LIMITING AN ACTIVE AREA

INTEGRATED CIRCUIT INCLUDING BALANCED CELLS LIMITING AN ACTIVE AREA

METHOD OF FORMING STRAINED MOS TRANSISTORS