Rengarajan S Krishnan

Person

Karnataka, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Fully digital, static, true single-phase clock (TSPC) flip-flop
- Patent number 10,840,892
- Issue date Nov 17, 2020
- Marvell Asia Pte, Ltd.
- Krishnan S. Rengarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 10,783,956
- Issue date Sep 22, 2020
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 10,783,958
- Issue date Sep 22, 2020
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Feed forward equalizer with power-optimized distributed arithmetic...
- Patent number 10,721,104
- Issue date Jul 21, 2020
- Marvell Asia Pte, Ltd.
- Krishnan S. Rengarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power scan flip-flop
- Patent number 10,659,017
- Issue date May 19, 2020
- Marvell International Ltd.
- Krishnan S. Rengarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scoped search engine
- Patent number 10,489,455
- Issue date Nov 26, 2019
- GLOBALFOUNDRIES U.S. INC.
- Samuel S. Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-demand feed forward equalizer with distributed arithmetic archit...
- Patent number 10,447,510
- Issue date Oct 15, 2019
- GLOBALFOUNDRIES Inc.
- Krishnan S. Rengarajan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Feed forward equalizer with power-optimized distributed arithmetic...
- Patent number 10,432,436
- Issue date Oct 1, 2019
- GLOBALFOUNDRIES Inc.
- Krishnan S. Rengarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tunable negative bit line write assist and boost attenuation circuit
- Patent number 10,319,431
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 10,217,510
- Issue date Feb 26, 2019
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 9,984,742
- Issue date May 29, 2018
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Minimization of bias temperature instability (BTI) degradation in c...
- Patent number 9,859,873
- Issue date Jan 2, 2018
- International Business Machines Corporation
- Navin Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 9,847,119
- Issue date Dec 19, 2017
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Disturb free bitcell and array
- Patent number 9,589,658
- Issue date Mar 7, 2017
- GLOBALFOUNDRIES INC.
- Navin Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit to improve SRAM stability
- Patent number 9,570,155
- Issue date Feb 14, 2017
- GLOBALFOUNDRIES Inc.
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Boost control to improve SRAM write operation
- Patent number 9,548,104
- Issue date Jan 17, 2017
- International Business Machines Corporation
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 9,496,025
- Issue date Nov 15, 2016
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Data-dependent self-biased differential sense amplifier
- Patent number 9,460,760
- Issue date Oct 4, 2016
- GlobalFoundries Inc.
- Balaji Jayaraman
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance sense amplifier
- Patent number 9,437,282
- Issue date Sep 6, 2016
- GLOBALFOUNDRIES INC.
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for defining a default state of a charge trap based memory cell
- Patent number 9,324,430
- Issue date Apr 26, 2016
- GLOBALFOUNDRIES Inc.
- Sheikh Sabiq Chishti
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power sense amplifier for static random access memory
- Patent number 9,286,969
- Issue date Mar 15, 2016
- GLOBALFOUNDRIES Inc.
- Pankaj Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Refresh hidden eDRAM memory
- Patent number 9,281,045
- Issue date Mar 8, 2016
- GLOBALFOUNDRIES Inc.
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Bias temperature instability state detection and correction
- Patent number 9,251,890
- Issue date Feb 2, 2016
- GLOBALFOUNDRIES Inc.
- Navin Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cells with read access schemes
- Patent number 9,236,116
- Issue date Jan 12, 2016
- GLOBALFOUNDRIES Inc.
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier for static random access memory with a pair of comp...
- Patent number 9,047,980
- Issue date Jun 2, 2015
- International Business Machines Corporation
- Pankaj Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Crosstalk compensation for high speed, reduced swing circuits
- Patent number 8,797,096
- Issue date Aug 5, 2014
- International Business Machines Corporation
- Prasad S. Nalawade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asymmetric memory cells
- Patent number 8,593,861
- Issue date Nov 26, 2013
- International Business Machines Corporation
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic wordline assist scheme to improve performance tradeoff in SRAM
- Patent number 8,427,896
- Issue date Apr 23, 2013
- International Business Machines Corporation
- Pankaj Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Reset circuit for termination of tracking circuits in self timed co...
- Patent number 7,755,949
- Issue date Jul 13, 2010
- Texas Instruments Incorporated
- Krishnan S Rengarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Match mismatch emulation scheme for an addressed location in a CAM
- Patent number 7,471,536
- Issue date Dec 30, 2008
- Texas Instruments Incorporated
- Rengarajan S Krishnan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LOW-POWER SCAN FLIP-FLOP
- Publication number 20200186131
- Publication date Jun 11, 2020
- GLOBALFOUNDRIES INC.
- Krishnan S. Rengarajan
- G01 - MEASURING TESTING
Information Patent Application
FEED FORWARD EQUALIZER WITH POWER-OPTIMIZED DISTRIBUTED ARITHMETIC...
- Publication number 20200186401
- Publication date Jun 11, 2020
- GLOBALFOUNDRIES INC.
- Krishnan S. Rengarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20190304536
- Publication date Oct 3, 2019
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20190147946
- Publication date May 16, 2019
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20180130522
- Publication date May 10, 2018
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20180068717
- Publication date Mar 8, 2018
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
DISTURB FREE BITCELL AND ARRAY
- Publication number 20170053705
- Publication date Feb 23, 2017
- GLOBALFOUNDRIES Inc.
- Navin AGARWAL
- G11 - INFORMATION STORAGE
Information Patent Application
BOOST CONTROL TO IMPROVE SRAM WRITE OPERATION
- Publication number 20170004874
- Publication date Jan 5, 2017
- International Business Machines Corporation
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20170004876
- Publication date Jan 5, 2017
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT TO IMPROVE SRAM STABILITY
- Publication number 20160365139
- Publication date Dec 15, 2016
- International Business Machines Corporation
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20160232966
- Publication date Aug 11, 2016
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
DATA-DEPENDENT SELF-BIASED DIFFERENTIAL SENSE AMPLIFIER
- Publication number 20160217832
- Publication date Jul 28, 2016
- GLOBALFOUNDRIES Inc.
- Balaji Jayaraman
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20160203857
- Publication date Jul 14, 2016
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
MINIMIZATION OF BIAS TEMPERATURE INSTABILITY (BTI) DEGRADATION IN C...
- Publication number 20160164497
- Publication date Jun 9, 2016
- International Business Machines Corporation
- Navin Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCOPED SEARCH ENGINE
- Publication number 20160140243
- Publication date May 19, 2016
- International Business Machines Corporation
- Samuel S. Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY
- Publication number 20150380079
- Publication date Dec 31, 2015
- International Business Machines Corporation
- Pankaj Agarwal
- G11 - INFORMATION STORAGE
Information Patent Application
Method For Defining A Default State of a Charge Trap Based Memory Cell
- Publication number 20150318043
- Publication date Nov 5, 2015
- International Business Machines Corporation
- Sheikh Sabiq Chishti
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY
- Publication number 20140036581
- Publication date Feb 6, 2014
- International Business Machines Corporation
- Pankaj Agarwal
- G11 - INFORMATION STORAGE
Information Patent Application
CROSSTALK COMPENSATION FOR HIGH SPEED, REDUCED SWING CIRCUITS
- Publication number 20130147547
- Publication date Jun 13, 2013
- International Business Machines Corporation
- Prasad S. NALAWADE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC WORDLINE ASSIST SCHEME TO IMPROVE PERFORMANCE TRADEOFF IN SRAM
- Publication number 20130121065
- Publication date May 16, 2013
- International Business Machines Corporation
- Pankaj Agarwal
- G11 - INFORMATION STORAGE
Information Patent Application
ASYMMETRIC MEMORY CELLS
- Publication number 20130088931
- Publication date Apr 11, 2013
- International Business Machines Corporation
- George M. BRACERAS
- G11 - INFORMATION STORAGE
Information Patent Application
RESET CIRCUIT FOR TERMINATION OF TRACKING CIRCUITS IN SELF TIMED CO...
- Publication number 20100046309
- Publication date Feb 25, 2010
- KRISHNAN S. RENGARAJAN
- G11 - INFORMATION STORAGE
Information Patent Application
NOVEL HIGH PERFORMANCE, AREA EFFICIENT DIRECT BITLINE SENSING CIRCUIT
- Publication number 20090147605
- Publication date Jun 11, 2009
- Krishnan S. Rengarajan
- G11 - INFORMATION STORAGE
Information Patent Application
NOVEL MATCH MISMATCH EMULATION SCHEME FOR AN ADDRESSED LOCATION IN...
- Publication number 20080137388
- Publication date Jun 12, 2008
- Rengarajan S. Krishnan
- G11 - INFORMATION STORAGE
Information Patent Application
MATCH SENSING CIRCUIT FOR A CONTENT ADDRESSABLE MEMORY DEVICE
- Publication number 20070242493
- Publication date Oct 18, 2007
- Nisha Padattil Kuliyampattil
- G11 - INFORMATION STORAGE
Information Patent Application
Recovering data encoded in serial communication channels
- Publication number 20030123573
- Publication date Jul 3, 2003
- TEXAS INSTRUMENTS INCORPORATED
- Krishnan Santhana Rengarajan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Rengarajan S Krishnan

Person

Patents Grantslast 30 patents

Fully digital, static, true single-phase clock (TSPC) flip-flop

Tunable negative bitline write assist and boost attenuation circuit

Tunable negative bitline write assist and boost attenuation circuit

Feed forward equalizer with power-optimized distributed arithmetic...

Low-power scan flip-flop

Scoped search engine

On-demand feed forward equalizer with distributed arithmetic archit...

Feed forward equalizer with power-optimized distributed arithmetic...

Tunable negative bit line write assist and boost attenuation circuit

Tunable negative bitline write assist and boost attenuation circuit

Tunable negative bitline write assist and boost attenuation circuit

Minimization of bias temperature instability (BTI) degradation in c...

Tunable negative bitline write assist and boost attenuation circuit

Disturb free bitcell and array

Circuit to improve SRAM stability

Boost control to improve SRAM write operation

Tunable negative bitline write assist and boost attenuation circuit

Data-dependent self-biased differential sense amplifier

High performance sense amplifier

Method for defining a default state of a charge trap based memory cell

Low power sense amplifier for static random access memory

Refresh hidden eDRAM memory

Bias temperature instability state detection and correction

Memory cells with read access schemes

Sense amplifier for static random access memory with a pair of comp...

Crosstalk compensation for high speed, reduced swing circuits

Asymmetric memory cells

Dynamic wordline assist scheme to improve performance tradeoff in SRAM

Reset circuit for termination of tracking circuits in self timed co...

Match mismatch emulation scheme for an addressed location in a CAM

Patents Applicationslast 30 patents

LOW-POWER SCAN FLIP-FLOP

FEED FORWARD EQUALIZER WITH POWER-OPTIMIZED DISTRIBUTED ARITHMETIC...

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

DISTURB FREE BITCELL AND ARRAY

BOOST CONTROL TO IMPROVE SRAM WRITE OPERATION

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

CIRCUIT TO IMPROVE SRAM STABILITY

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

DATA-DEPENDENT SELF-BIASED DIFFERENTIAL SENSE AMPLIFIER

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

MINIMIZATION OF BIAS TEMPERATURE INSTABILITY (BTI) DEGRADATION IN C...

SCOPED SEARCH ENGINE

LOW POWER SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY

Method For Defining A Default State of a Charge Trap Based Memory Cell

SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY

CROSSTALK COMPENSATION FOR HIGH SPEED, REDUCED SWING CIRCUITS

DYNAMIC WORDLINE ASSIST SCHEME TO IMPROVE PERFORMANCE TRADEOFF IN SRAM

ASYMMETRIC MEMORY CELLS

RESET CIRCUIT FOR TERMINATION OF TRACKING CIRCUITS IN SELF TIMED CO...

NOVEL HIGH PERFORMANCE, AREA EFFICIENT DIRECT BITLINE SENSING CIRCUIT

NOVEL MATCH MISMATCH EMULATION SCHEME FOR AN ADDRESSED LOCATION IN...

MATCH SENSING CIRCUIT FOR A CONTENT ADDRESSABLE MEMORY DEVICE

Recovering data encoded in serial communication channels