Reza A. Pagaila

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method of forming Fo-WLCSP with recessed i...
- Patent number 10,388,584
- Issue date Aug 20, 2019
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system and method of manufacture thereof
- Patent number 10,043,733
- Issue date Aug 7, 2018
- STATS ChipPAC Pte. Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interposer with opening...
- Patent number 9,875,911
- Issue date Jan 23, 2018
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming anisotropic conductive f...
- Patent number 9,620,455
- Issue date Apr 11, 2017
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming openings in thermally-co...
- Patent number 9,508,626
- Issue date Nov 29, 2016
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming EMI shielding layer with...
- Patent number 9,484,279
- Issue date Nov 1, 2016
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming channels in back surface...
- Patent number 9,431,316
- Issue date Aug 30, 2016
- STATS ChipPAC Pte. Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming B-stage conductive polym...
- Patent number 9,418,941
- Issue date Aug 16, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including pre-fabricated shielding frame dispo...
- Patent number 9,406,619
- Issue date Aug 2, 2016
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming double-sided through via...
- Patent number 9,343,429
- Issue date May 17, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming stepped interposer for s...
- Patent number 9,337,116
- Issue date May 10, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming dual-active sided semico...
- Patent number 9,324,672
- Issue date Apr 26, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
RDL patterning with package on package system
- Patent number 9,293,385
- Issue date Mar 22, 2016
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming Fo-WLCSP with discrete s...
- Patent number 9,263,301
- Issue date Feb 16, 2016
- STARS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a vertical interconnect structure using...
- Patent number 9,263,361
- Issue date Feb 16, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die and method of forming noise absorbing regions bet...
- Patent number 9,236,352
- Issue date Jan 12, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of stacking die on leadframe electr...
- Patent number 9,177,901
- Issue date Nov 3, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming base substrate with cavi...
- Patent number 9,142,431
- Issue date Sep 22, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with exposed vertical interconn...
- Patent number 9,093,364
- Issue date Jul 28, 2015
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of mounting die with TSV in cavity...
- Patent number 9,064,876
- Issue date Jun 23, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Exposed interconnect for a package on package system
- Patent number 9,059,011
- Issue date Jun 16, 2015
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming WLP with semiconductor d...
- Patent number 9,054,095
- Issue date Jun 9, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system having planar interconnect and...
- Patent number 9,029,205
- Issue date May 12, 2015
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with internal stacking module
- Patent number 9,030,006
- Issue date May 12, 2015
- Stats Chippac Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming recessed conductive vias...
- Patent number 9,006,882
- Issue date Apr 14, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming thermally conductive lay...
- Patent number 8,999,760
- Issue date Apr 7, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit packaging system for electromagnetic interferenc...
- Patent number 8,969,136
- Issue date Mar 3, 2015
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with heat shield and method of...
- Patent number 8,962,393
- Issue date Feb 24, 2015
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming stepped interconnect lay...
- Patent number 8,946,870
- Issue date Feb 3, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Through hole vias at saw streets including protrusions or recesses...
- Patent number 8,940,636
- Issue date Jan 27, 2015
- STATS ChipPAC, Ltc.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Device and Method of Forming Sacrificial Adhesive Ove...
- Publication number 20140252631
- Publication date Sep 11, 2014
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METH...
- Publication number 20130214430
- Publication date Aug 22, 2013
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Conductive TSV With Insu...
- Publication number 20130087928
- Publication date Apr 11, 2013
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming a Shielding Layer Betwee...
- Publication number 20130087897
- Publication date Apr 11, 2013
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Different Height Conduct...
- Publication number 20130075903
- Publication date Mar 28, 2013
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SHIELD AND METHOD OF...
- Publication number 20130075889
- Publication date Mar 28, 2013
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device and method of forming FO-WLCSP with recessed i...
- Publication number 20130056867
- Publication date Mar 7, 2013
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Base Substrate with Cavi...
- Publication number 20130015577
- Publication date Jan 17, 2013
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming FO-WLCSP with Discrete S...
- Publication number 20130001771
- Publication date Jan 3, 2013
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD O...
- Publication number 20120326281
- Publication date Dec 27, 2012
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METH...
- Publication number 20120319262
- Publication date Dec 20, 2012
- Heap Hoe Kuan
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM
- Publication number 20120306078
- Publication date Dec 6, 2012
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Shielding Layer Over Sem...
- Publication number 20120299165
- Publication date Nov 29, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE
- Publication number 20120292750
- Publication date Nov 22, 2012
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Mounting Die with TSV in Cavity...
- Publication number 20120292785
- Publication date Nov 22, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Discontinuous ESD Protec...
- Publication number 20120292749
- Publication date Nov 22, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Dual-Molding Die Formed on Oppos...
- Publication number 20120286404
- Publication date Nov 15, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF...
- Publication number 20120286432
- Publication date Nov 15, 2012
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Die and Method of Forming through Organic Vias having...
- Publication number 20120280403
- Publication date Nov 8, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Die and Method of Forming through Organic Vias having...
- Publication number 20120280402
- Publication date Nov 8, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Shielding Layer Over Act...
- Publication number 20120273926
- Publication date Nov 1, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Embedding Bumps Formed on Semico...
- Publication number 20120261818
- Publication date Oct 18, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Thermally Conductive Lay...
- Publication number 20120248596
- Publication date Oct 4, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM FOR ELECTROMAGNETIC INTERFERENC...
- Publication number 20120241922
- Publication date Sep 27, 2012
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF...
- Publication number 20120241973
- Publication date Sep 27, 2012
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus for Thermally Enhanced Semiconductor Package
- Publication number 20120241939
- Publication date Sep 27, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Embedding Thermally Conductive L...
- Publication number 20120241940
- Publication date Sep 27, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM USING B-STAGE POLYMER AND METHO...
- Publication number 20120228768
- Publication date Sep 13, 2012
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER SEM...
- Publication number 20120228749
- Publication date Sep 13, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interposer and Opposing...
- Publication number 20120217645
- Publication date Aug 30, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Reza A. Pagaila

Person

Patents Grantslast 30 patents

Semiconductor device and method of forming Fo-WLCSP with recessed i...

Integrated circuit packaging system and method of manufacture thereof

Semiconductor device and method of forming interposer with opening...

Semiconductor device and method of forming anisotropic conductive f...

Semiconductor device and method of forming openings in thermally-co...

Semiconductor device and method of forming EMI shielding layer with...

Semiconductor device and method of forming channels in back surface...

Semiconductor device and method of forming B-stage conductive polym...

Semiconductor device including pre-fabricated shielding frame dispo...

Semiconductor device and method of forming double-sided through via...

Semiconductor device and method of forming stepped interposer for s...

Semiconductor device and method of forming dual-active sided semico...

RDL patterning with package on package system

Semiconductor device and method of forming Fo-WLCSP with discrete s...

Semiconductor device having a vertical interconnect structure using...

Semiconductor die and method of forming noise absorbing regions bet...

Semiconductor device and method of stacking die on leadframe electr...

Semiconductor device and method of forming base substrate with cavi...

Integrated circuit packaging system with exposed vertical interconn...

Semiconductor device and method of mounting die with TSV in cavity...

Exposed interconnect for a package on package system

Semiconductor device and method of forming WLP with semiconductor d...

Integrated circuit packaging system having planar interconnect and...

Integrated circuit package system with internal stacking module

Semiconductor device and method of forming recessed conductive vias...

Semiconductor device and method of forming thermally conductive lay...

Integrated circuit packaging system for electromagnetic interferenc...

Integrated circuit packaging system with heat shield and method of...

Semiconductor device and method of forming stepped interconnect lay...

Through hole vias at saw streets including protrusions or recesses...

Patents Applicationslast 30 patents

Semiconductor Device and Method of Forming Sacrificial Adhesive Ove...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METH...

Semiconductor Device and Method of Forming Conductive TSV With Insu...

Semiconductor Device and Method of Forming a Shielding Layer Betwee...

Semiconductor Device and Method of Forming Different Height Conduct...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SHIELD AND METHOD OF...

Semiconductor device and method of forming FO-WLCSP with recessed i...

Semiconductor Device and Method of Forming Base Substrate with Cavi...

Semiconductor Device and Method of Forming FO-WLCSP with Discrete S...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD O...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METH...

EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM

Semiconductor Device and Method of Forming Shielding Layer Over Sem...

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE

Semiconductor Device and Method of Mounting Die with TSV in Cavity...

Semiconductor Device and Method of Forming Discontinuous ESD Protec...

Semiconductor Device and Method of Dual-Molding Die Formed on Oppos...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF...

Semiconductor Die and Method of Forming through Organic Vias having...

Semiconductor Die and Method of Forming through Organic Vias having...

Semiconductor Device and Method of Forming Shielding Layer Over Act...

Semiconductor Device and Method of Embedding Bumps Formed on Semico...

Semiconductor Device and Method of Forming Thermally Conductive Lay...

INTEGRATED CIRCUIT PACKAGING SYSTEM FOR ELECTROMAGNETIC INTERFERENC...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF...

Apparatus for Thermally Enhanced Semiconductor Package

Semiconductor Device and Method of Embedding Thermally Conductive L...

INTEGRATED CIRCUIT PACKAGING SYSTEM USING B-STAGE POLYMER AND METHO...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER SEM...

Semiconductor Device and Method of Forming Interposer and Opposing...