Reza Tusi

Person

San Jose, CA, US

People

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR INSTRUCTION-SET AWARE ARITHMETIC CODING FOR...
- Publication number 20250138822
- Publication date May 1, 2025
- Meta Platforms Technologies, LLC
- Reza Tusi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PARALLELISM
- Publication number 20240220255
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Reza Tusi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAPPING HARDWARE COMPONENTS TO A SERIES OF CALCULATIONS
- Publication number 20240220281
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Vignesh Vivekraja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DSP BASED COMPUTE ENGINE FOR EXECUTING MATRIX OPERATIONS
- Publication number 20240220574
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Shiyu Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ARCHITECTURE AND AN INSTRUCTION SET ARCHITECTURE FOR MACHI...
- Publication number 20240220273
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Vignesh Vivekraja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POLYMORPHIC TWO-DIMENSIONAL REGISTER FILE
- Publication number 20240220256
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Reza Tusi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENCE OF OPERATIONS IN AN SIMD VLIW PROCESSOR FOR MACHINE-LEARNI...
- Publication number 20240220779
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Vignesh Vivekraja
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR INSTRUCTION-SET AWARE ARITHMETIC CODING FOR...

DATA PARALLELISM

MAPPING HARDWARE COMPONENTS TO A SERIES OF CALCULATIONS

DSP BASED COMPUTE ENGINE FOR EXECUTING MATRIX OPERATIONS

HARDWARE ARCHITECTURE AND AN INSTRUCTION SET ARCHITECTURE FOR MACHI...

POLYMORPHIC TWO-DIMENSIONAL REGISTER FILE

SEQUENCE OF OPERATIONS IN AN SIMD VLIW PROCESSOR FOR MACHINE-LEARNI...