Rich Modelski

Person

Hollis, NH, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for efficient loop instruction execution using...
- Patent number 9,152,423
- Issue date Oct 6, 2015
- Avaya Inc.
- Hamid Assarpour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficient memory bank utilization in multi...
- Patent number 8,832,350
- Issue date Sep 9, 2014
- Avaya Inc.
- Hamid Assarpour
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-thread packet processor
- Patent number 8,762,581
- Issue date Jun 24, 2014
- Avaya Inc.
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing filter operations on data packe...
- Patent number 7,369,554
- Issue date May 6, 2008
- Nortel Networks Limited
- Richard P. Modelski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for monitoring a network using statistical inf...
- Patent number 7,293,079
- Issue date Nov 6, 2007
- Nortel Networks Limited
- Adrian M. Kristiansen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for sharing a computer resource between instructi...
- Patent number 7,131,125
- Issue date Oct 31, 2006
- Nortel Networks Limited
- Richard P. Modelski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Load-shift carry instruction
- Patent number 7,069,422
- Issue date Jun 27, 2006
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing a radix search by selecting one...
- Patent number 7,039,627
- Issue date May 2, 2006
- Nortel Networks Limited
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit field manipulation
- Patent number 7,013,302
- Issue date Mar 14, 2006
- Nortel Networks Limited
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global access bus architecture
- Patent number 6,981,077
- Issue date Dec 27, 2005
- Nortel Networks Limited
- Richard P. Modelski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
External memory engine selectable pipeline architecture
- Patent number 6,934,780
- Issue date Aug 23, 2005
- Nortel Networks Limited
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed physical circuits of memory interface
- Patent number 6,847,640
- Issue date Jan 25, 2005
- Nortel Networks Limited
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed access bus interface and protocol
- Patent number 6,778,526
- Issue date Aug 17, 2004
- Nortel Networks Limited
- Benjamin J. Brown
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Centralized look up engine architecture and interface
- Patent number 6,772,268
- Issue date Aug 3, 2004
- Nortel Networks Ltd.
- Adrian Kristiansen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Extended double word accesses
- Patent number 6,684,300
- Issue date Jan 27, 2004
- Nortel Networks Limited
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
External memory engine selectable pipeline architecture
- Patent number 6,665,755
- Issue date Dec 16, 2003
- Nortel Networks Limited
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing distinct types of radix searches
- Patent number 6,633,880
- Issue date Oct 14, 2003
- Nortel Networks Limited
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR EFFICIENT LOOP INSTRUCTION EXECUTION USING...
- Publication number 20120246449
- Publication date Sep 27, 2012
- AVAYA INC.
- Hamid Assarpour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING POLICING OPERATIONS IN PACKET TIME
- Publication number 20120127864
- Publication date May 24, 2012
- AVAYA INC.
- Hamid Assarpour
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and Apparatus for Efficient Memory Bank Utilization in Multi...
- Publication number 20110320680
- Publication date Dec 29, 2011
- AVAYA INC.
- Hamid Assarpour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
External memory engine selectable pipeline architecture
- Publication number 20050076169
- Publication date Apr 7, 2005
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Global access bus architecture
- Publication number 20020120798
- Publication date Aug 29, 2002
- Richard P. Modelski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Bit field manipulation
- Publication number 20020120828
- Publication date Aug 29, 2002
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Route switch packet architecture
- Publication number 20020116442
- Publication date Aug 22, 2002
- Richard P. Modelski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Load-shift carry instruction
- Publication number 20020116449
- Publication date Aug 22, 2002
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
External memory engine selectable pipeline architecture
- Publication number 20020116587
- Publication date Aug 22, 2002
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-thread packet processor
- Publication number 20020083297
- Publication date Jun 27, 2002
- Richard P. Modelski
- G06 - COMPUTING CALCULATING COUNTING

Rich Modelski

Person

Patents Grantslast 30 patents

Method and apparatus for efficient loop instruction execution using...

Method and apparatus for efficient memory bank utilization in multi...

Multi-thread packet processor

Method and apparatus for performing filter operations on data packe...

Method and apparatus for monitoring a network using statistical inf...

Method and system for sharing a computer resource between instructi...

Load-shift carry instruction

Method and apparatus for performing a radix search by selecting one...

Bit field manipulation

Global access bus architecture

External memory engine selectable pipeline architecture

High speed physical circuits of memory interface

High speed access bus interface and protocol

Centralized look up engine architecture and interface

Extended double word accesses

External memory engine selectable pipeline architecture

Method and apparatus for performing distinct types of radix searches

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR EFFICIENT LOOP INSTRUCTION EXECUTION USING...

PERFORMING POLICING OPERATIONS IN PACKET TIME

Method and Apparatus for Efficient Memory Bank Utilization in Multi...

External memory engine selectable pipeline architecture

Global access bus architecture

Bit field manipulation

Route switch packet architecture

Load-shift carry instruction

External memory engine selectable pipeline architecture

Multi-thread packet processor