Richard A. Carberry

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Double data rate flip-flop
- Patent number 7,317,773
- Issue date Jan 8, 2008
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Double data rate flip-flop
- Patent number 6,777,980
- Issue date Aug 17, 2004
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
FPGA lookup table with high speed read decorder
- Patent number 6,621,296
- Issue date Sep 16, 2003
- Xilinx, Inc.
- Richard A. Carberry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA lookup table with speed read decoder
- Patent number 6,529,040
- Issue date Mar 4, 2003
- Xilinx, Inc.
- Richard A. Carberry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Double data rate flip-flop
- Patent number 6,525,565
- Issue date Feb 25, 2003
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Logic/memory circuit having a plurality of operating modes
- Patent number 6,501,296
- Issue date Dec 31, 2002
- Xilinx, Inc.
- Ralph D. Wittig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of time multiplexing a programmable logic device
- Patent number 6,480,954
- Issue date Nov 12, 2002
- Xilinx Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA lookup table with NOR gate write decoder and high speed read d...
- Patent number 6,445,209
- Issue date Sep 3, 2002
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA lookup table with dual ended writes for ram and shift register...
- Patent number 6,373,279
- Issue date Apr 16, 2002
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device having configurable logic blocks with use...
- Patent number 6,292,019
- Issue date Sep 18, 2001
- Xilinx Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory array with hard and soft decoders
- Patent number 6,288,569
- Issue date Sep 11, 2001
- Xilinx, Inc.
- Ralph D. Wittig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of time multiplexing a programmable logic device
- Patent number 6,263,430
- Issue date Jul 17, 2001
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA configurable logic block with multi-purpose logic/memory circuit
- Patent number 6,208,163
- Issue date Mar 27, 2001
- Xilinx, Inc.
- Ralph D. Wittig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA configurable logic block with multi-purpose logic/memory circuit
- Patent number 6,184,712
- Issue date Feb 6, 2001
- Xilinx, Inc.
- Ralph D. Wittig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA configurable logic block with multi-purpose logic/memory circuit
- Patent number 6,150,838
- Issue date Nov 21, 2000
- Xilinx, Inc.
- Ralph D. Wittig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay control circuit using dynamic latches
- Patent number 6,078,528
- Issue date Jun 20, 2000
- Xilinx, Inc.
- Robert Anders Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of time multiplexing a programmable logic device
- Patent number 5,978,260
- Issue date Nov 2, 1999
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device including configuration data or user data...
- Patent number 5,959,881
- Issue date Sep 28, 1999
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RAM with synchronous write port using dynamic latches
- Patent number 5,933,369
- Issue date Aug 3, 1999
- Xilinx, Inc.
- Robert Anders Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device including configuration data or user data...
- Patent number 5,784,313
- Issue date Jul 21, 1998
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with hierarchical confiquration and state...
- Patent number 5,778,439
- Issue date Jul 7, 1998
- Xilinx, Inc.
- Stephen M. Trimberger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Time multiplexed programmable logic device
- Patent number 5,646,545
- Issue date Jul 8, 1997
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of time multiplexing a programmable logic device
- Patent number 5,629,637
- Issue date May 13, 1997
- Xilinx, Inc.
- Stephen M. Trimberger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuration modes for a time multiplexed programmable logic device
- Patent number 5,600,263
- Issue date Feb 4, 1997
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequencer for a time multiplexed programmable logic device
- Patent number 5,583,450
- Issue date Dec 10, 1996
- Xilinx, Inc.
- Stephen M. Trimberger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input synchronization mechanism for inside/outside clock
- Patent number 5,578,946
- Issue date Nov 26, 1996
- Xilinx, Inc.
- Richard A. Carberry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined single chip microprocessor having on-chip cache and on-ch...
- Patent number 4,794,524
- Issue date Dec 27, 1988
- Zilog, Inc.
- Richard A. Carberry
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Double data rate flip-flop
- Publication number 20040239365
- Publication date Dec 2, 2004
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Double data rate flip-flop
- Publication number 20030112032
- Publication date Jun 19, 2003
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
FPGA lookup table with high speed read decoder
- Publication number 20030071653
- Publication date Apr 17, 2003
- Xilinx, Inc.
- Richard A. Carberry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Double data rate flip-flop
- Publication number 20020175704
- Publication date Nov 28, 2002
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method of time multiplexing a programmable logic device
- Publication number 20020010853
- Publication date Jan 24, 2002
- Xilinx, Inc.
- Stephen M. Trimberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic/memory circuit having a plurality of operating modes
- Publication number 20010043082
- Publication date Nov 22, 2001
- Xilink, Inc.
- Ralph D. Wittig
- H03 - BASIC ELECTRONIC CIRCUITRY

Richard A. Carberry

Person

Patents Grantslast 30 patents

Double data rate flip-flop

Double data rate flip-flop

FPGA lookup table with high speed read decorder

FPGA lookup table with speed read decoder

Double data rate flip-flop

Logic/memory circuit having a plurality of operating modes

Method of time multiplexing a programmable logic device

FPGA lookup table with NOR gate write decoder and high speed read d...

FPGA lookup table with dual ended writes for ram and shift register...

Programmable logic device having configurable logic blocks with use...

Memory array with hard and soft decoders

Method of time multiplexing a programmable logic device

FPGA configurable logic block with multi-purpose logic/memory circuit

FPGA configurable logic block with multi-purpose logic/memory circuit

FPGA configurable logic block with multi-purpose logic/memory circuit

Delay control circuit using dynamic latches

Method of time multiplexing a programmable logic device

Programmable logic device including configuration data or user data...

RAM with synchronous write port using dynamic latches

Programmable logic device including configuration data or user data...

Programmable logic device with hierarchical confiquration and state...

Time multiplexed programmable logic device

Method of time multiplexing a programmable logic device

Configuration modes for a time multiplexed programmable logic device

Sequencer for a time multiplexed programmable logic device

Input synchronization mechanism for inside/outside clock

Pipelined single chip microprocessor having on-chip cache and on-ch...

Patents Applicationslast 30 patents

Double data rate flip-flop

Double data rate flip-flop

FPGA lookup table with high speed read decoder

Double data rate flip-flop

Method of time multiplexing a programmable logic device

Logic/memory circuit having a plurality of operating modes