Richard A. Lemay

Person

Carlisle, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Executing programs of a first system on a second system
- Patent number 5,983,012
- Issue date Nov 9, 1999
- Bull HN Information Systems Inc.
- Richard S. Bianchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of optimizing the execution of program instuctions by an emu...
- Patent number 5,678,032
- Issue date Oct 14, 1997
- Bull HN Information Systems Inc.
- William E. Woods
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-on sequencing apparatus for initializing and testing a system...
- Patent number 5,491,790
- Issue date Feb 13, 1996
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable system bus priority network
- Patent number 5,446,847
- Issue date Aug 29, 1995
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for organizing state machine by selectively grouping status...
- Patent number 5,375,248
- Issue date Dec 20, 1994
- Bull HN Information Systems Inc.
- Richard A. Lemay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor bus access
- Patent number 5,341,501
- Issue date Aug 23, 1994
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus controller having state machine for translating commands and co...
- Patent number 5,341,495
- Issue date Aug 23, 1994
- Bull HN Information Systems, Inc.
- Thomas F. Joyce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor bus interface protocol analyzer
- Patent number 5,293,384
- Issue date Mar 8, 1994
- Bull HN Information Systems Inc.
- James W. Keeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance burst read data transfer operation
- Patent number 5,291,580
- Issue date Mar 1, 1994
- Bull HN Information Systems Inc.
- Raymond D. Bowden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State machine for executing commands within a minimum number of cyc...
- Patent number 5,280,595
- Issue date Jan 18, 1994
- Bull HN Information Systems Inc.
- Richard A. Lemay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor vectored interrupts
- Patent number 5,274,825
- Issue date Dec 28, 1993
- Bull HN Information Systems Inc.
- Richard A. Lemay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recovery method and apparatus for a pipelined processing unit of a...
- Patent number 5,193,181
- Issue date Mar 9, 1993
- Bull HN Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffered address stack register with parallel input registers and o...
- Patent number 5,161,217
- Issue date Nov 3, 1992
- Bull HN Information Systems Inc.
- Richard A. Lemay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level priority arbiter generating a request to the second level...
- Patent number 5,142,682
- Issue date Aug 25, 1992
- Bull HN Information Systems Inc.
- Richard Lemay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple shared memory arrangement wherein multiple processors indi...
- Patent number 5,136,500
- Issue date Aug 4, 1992
- Honeywell Information Systems Inc.
- Richard A. Lemay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory addressing arrangement
- Patent number 4,964,037
- Issue date Oct 16, 1990
- Bull HN Information Systems Inc.
- William E. Woods
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data selection matrix
- Patent number 4,935,737
- Issue date Jun 19, 1990
- Bull HN Information Systems Inc.
- Kenneth J. Izbicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bank selection arrangement generating first bits identifying...
- Patent number 4,903,197
- Issue date Feb 20, 1990
- Bull HN Information Systems Inc.
- David A. Wallace
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage of input/output command timeout and acknowledge responses
- Patent number 4,872,110
- Issue date Oct 3, 1989
- Bull HN Information Systems Inc.
- Michael D. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address boundary detector
- Patent number 4,837,738
- Issue date Jun 6, 1989
- Honeywell Information Systems Inc.
- Richard A. Lemay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multifunction arithmetic indicator
- Patent number 4,811,266
- Issue date Mar 7, 1989
- Honeywell Bull Inc.
- William E. Woods
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory failure detection apparatus
- Patent number 4,809,276
- Issue date Feb 28, 1989
- Hutton/PRC Technology Partners 1
- Richard A. Lemay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Time partitioned bus arrangement
- Patent number 4,775,929
- Issue date Oct 4, 1988
- Honeywell Bull Inc.
- Kenneth J. Izbicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware demand fetch cycle system interface
- Patent number 4,727,486
- Issue date Feb 23, 1988
- Honeywell Information Systems Inc.
- Michael D. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two stage selection based on time of arrival and predetermined prio...
- Patent number 4,604,685
- Issue date Aug 5, 1986
- Honeywell Information Systems Inc.
- Richard P. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction decoding logic system
- Patent number 4,472,773
- Issue date Sep 18, 1984
- Honeywell Information Systems Inc.
- Philip E. Stanley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic transfer and decoding system
- Patent number 4,467,416
- Issue date Aug 21, 1984
- Honeywell Information Systems Inc.
- David E. Cushing
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible logic transfer and instruction decoding system
- Patent number 4,467,417
- Issue date Aug 21, 1984
- Honeywell Information Systems Inc.
- William E. Woods
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic control system including cache memory for CPU-memory transfers
- Patent number 4,460,959
- Issue date Jul 17, 1984
- Honeywell Information Systems Inc.
- Richard A. Lemay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic control system for efficient memory to CPU transfers
- Patent number 4,455,606
- Issue date Jun 19, 1984
- Honeywell Information Systems Inc.
- David E. Cushing
- G06 - COMPUTING CALCULATING COUNTING

Richard A. Lemay

Person

Patents Grantslast 30 patents

Executing programs of a first system on a second system

Method of optimizing the execution of program instuctions by an emu...

Power-on sequencing apparatus for initializing and testing a system...

Programmable system bus priority network

Method for organizing state machine by selectively grouping status...

Processor bus access

Bus controller having state machine for translating commands and co...

Microprocessor bus interface protocol analyzer

High performance burst read data transfer operation

State machine for executing commands within a minimum number of cyc...

Microprocessor vectored interrupts

Recovery method and apparatus for a pipelined processing unit of a...

Buffered address stack register with parallel input registers and o...

Two-level priority arbiter generating a request to the second level...

Multiple shared memory arrangement wherein multiple processors indi...

Memory addressing arrangement

Data selection matrix

Memory bank selection arrangement generating first bits identifying...

Storage of input/output command timeout and acknowledge responses

Address boundary detector

Multifunction arithmetic indicator

Memory failure detection apparatus

Time partitioned bus arrangement

Hardware demand fetch cycle system interface

Two stage selection based on time of arrival and predetermined prio...

Instruction decoding logic system

Logic transfer and decoding system

Flexible logic transfer and instruction decoding system

Logic control system including cache memory for CPU-memory transfers

Logic control system for efficient memory to CPU transfers