Richard A. Relph

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Monitoring of memory page transitions between a hypervisor and a vi...
- Patent number 10,671,422
- Issue date Jun 2, 2020
- Advanced Micro Devices, Inc.
- David Kaplan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable 16 or 32 bit PCI interface which supports steering and swa...
- Patent number 6,393,548
- Issue date May 21, 2002
- Advanced Micro Devices, Inc.
- Denise Kerstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analog delay line implemented with a digital delay line technique
- Patent number 6,218,880
- Issue date Apr 17, 2001
- Legerity
- Richard Relph
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for using a memory management unit to reduce memo...
- Patent number 6,092,171
- Issue date Jul 18, 2000
- Advanced Micro Devices, Inc.
- Richard A. Relph
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-clocked logic circuit and methodology
- Patent number 6,064,232
- Issue date May 16, 2000
- Advanced Micro Devices, Inc.
- Richard Relph
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable delay line
- Patent number 6,046,620
- Issue date Apr 4, 2000
- Advanced Micro Devices, Inc.
- Richard Relph
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Floating point timer
- Patent number 5,903,521
- Issue date May 11, 1999
- Advanced Micro Devices, Inc.
- Richard A. Relph
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MONITORING OF MEMORY PAGE TRANSITIONS BETWEEN A HYPERVISOR AND A VI...
- Publication number 20180285140
- Publication date Oct 4, 2018
- Advanced Micro Devices, Inc.
- David KAPLAN
- G06 - COMPUTING CALCULATING COUNTING

Richard A. Relph

Person

Patents Grantslast 30 patents

Monitoring of memory page transitions between a hypervisor and a vi...

Variable 16 or 32 bit PCI interface which supports steering and swa...

Analog delay line implemented with a digital delay line technique

System and method for using a memory management unit to reduce memo...

Self-clocked logic circuit and methodology

Programmable delay line

Floating point timer

Patents Applicationslast 30 patents

MONITORING OF MEMORY PAGE TRANSITIONS BETWEEN A HYPERVISOR AND A VI...