Richard D. Blinne

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Unified layer stack architecture
- Patent number 7,853,901
- Issue date Dec 14, 2010
- LSI Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of automating place and route corrections for an integrated...
- Patent number 7,302,654
- Issue date Nov 27, 2007
- LSI Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental dummy metal insertions
- Patent number 7,260,803
- Issue date Aug 21, 2007
- LSI Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of implementing an engineering change order in an integrated...
- Patent number 7,231,626
- Issue date Jun 12, 2007
- LSI Corporation
- Jason K. Hoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for verifying an incremental change to...
- Patent number 7,219,317
- Issue date May 15, 2007
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comparison of two hierarchical netlist to generate change orders fo...
- Patent number 7,111,269
- Issue date Sep 19, 2006
- LSI Logic Corporation
- Lalita Satapathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of partitioning an integrated circuit design for physical de...
- Patent number 7,107,559
- Issue date Sep 12, 2006
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing engineering change orders
- Patent number 7,007,248
- Issue date Feb 28, 2006
- LSI Logic Corporation
- Richard Blinne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of repeater insertion for hierarchical integrated circuit de...
- Patent number 6,662,349
- Issue date Dec 9, 2003
- LSI Logic Corporation
- David A. Morgan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulse rejection circuit model program and technique in VHDL
- Patent number 6,141,631
- Issue date Oct 31, 2000
- LSI Logic Corporation
- Richard D. Blinne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating format-independent electronic circuit represe...
- Patent number 5,995,730
- Issue date Nov 30, 1999
- LSI Logic Corporation
- Richard D. Blinne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for calculating dynamic power dissipation in C...
- Patent number 5,521,834
- Issue date May 28, 1996
- AT&T Global Information Solutions Company
- Harold S. Crafts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of estimating logic cell delay time
- Patent number 5,274,568
- Issue date Dec 28, 1993
- NCR Corporation
- Richard D. Blinne
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Unified Layer Stack Architecture
- Publication number 20090271755
- Publication date Oct 29, 2009
- LSI Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of implementing an engineering change order in an integrated...
- Publication number 20060136855
- Publication date Jun 22, 2006
- LSI Logic Corporation
- Jason K. Hoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of automating place and route corrections for an integrated...
- Publication number 20060095883
- Publication date May 4, 2006
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of automating place and route corrections for an integrated...
- Publication number 20060090144
- Publication date Apr 27, 2006
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and computer program for verifying an incremental change to...
- Publication number 20050235234
- Publication date Oct 20, 2005
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of partitioning an integrated circuit design for physical de...
- Publication number 20050097488
- Publication date May 5, 2005
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Comparison of two hierarchical netlist to generate change orders fo...
- Publication number 20050091627
- Publication date Apr 28, 2005
- Lalita Satapathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Incremental dummy metal insertions
- Publication number 20050080607
- Publication date Apr 14, 2005
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for implementing engineering change orders
- Publication number 20040230920
- Publication date Nov 18, 2004
- Richard Blinne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of repeater insertion for hierarchical integrated circuit de...
- Publication number 20030163795
- Publication date Aug 28, 2003
- David A. Morgan
- G06 - COMPUTING CALCULATING COUNTING

Richard D. Blinne

Person

Patents Grantslast 30 patents

Unified layer stack architecture

Method of automating place and route corrections for an integrated...

Incremental dummy metal insertions

Method of implementing an engineering change order in an integrated...

Method and computer program for verifying an incremental change to...

Comparison of two hierarchical netlist to generate change orders fo...

Method of partitioning an integrated circuit design for physical de...

Method and apparatus for implementing engineering change orders

Method of repeater insertion for hierarchical integrated circuit de...

Pulse rejection circuit model program and technique in VHDL

Method for generating format-independent electronic circuit represe...

Method and apparatus for calculating dynamic power dissipation in C...

Method of estimating logic cell delay time

Patents Applicationslast 30 patents

Unified Layer Stack Architecture

Method of implementing an engineering change order in an integrated...

Method of automating place and route corrections for an integrated...

Method of automating place and route corrections for an integrated...

Method and computer program for verifying an incremental change to...

Method of partitioning an integrated circuit design for physical de...

Comparison of two hierarchical netlist to generate change orders fo...

Incremental dummy metal insertions

Method and apparatus for implementing engineering change orders

Method of repeater insertion for hierarchical integrated circuit de...