Richard D. Pribnow

Person

Chippewa Falls, WI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Message buffering for a computer-based network
- Patent number 6,256,677
- Issue date Jul 3, 2001
- Silicon Graphics, Inc.
- Richard D. Pribnow
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Adaptive congestion control mechanism for modular computer networks
- Patent number 5,958,017
- Issue date Sep 28, 1999
- Cray Research, Inc.
- Steven L. Scott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive congestion control mechanism for modular computer networks
- Patent number 5,748,900
- Issue date May 5, 1998
- Cray Research, Inc.
- Steven L. Scott
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable spare memory chips
- Patent number 5,392,292
- Issue date Feb 21, 1995
- Cray Research, Inc.
- Thomas J. Davis
- G11 - INFORMATION STORAGE
Information Patent Grant
Real time I/O operation in a vector processing computer system by r...
- Patent number 5,390,300
- Issue date Feb 14, 1995
- Cray Research, Inc.
- Richard D. Pribnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disabled memory sections for degraded operation of a vector superco...
- Patent number 5,327,550
- Issue date Jul 5, 1994
- Cray Research, Inc.
- Richard D. Pribnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory range monitoring apparatus for a multiprocessor computer system
- Patent number 5,295,260
- Issue date Mar 15, 1994
- Cray Research Systems, Inc.
- Richard D. Pribnow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for multiprocessor communication using local and common sema...
- Patent number 4,754,398
- Issue date Jun 28, 1988
- Cray Research, Inc.
- Richard D. Pribnow
- G06 - COMPUTING CALCULATING COUNTING

Richard D. Pribnow

Person

Patents Grantslast 30 patents

Message buffering for a computer-based network

Adaptive congestion control mechanism for modular computer networks

Adaptive congestion control mechanism for modular computer networks

Configurable spare memory chips

Real time I/O operation in a vector processing computer system by r...

Disabled memory sections for degraded operation of a vector superco...

Memory range monitoring apparatus for a multiprocessor computer system

System for multiprocessor communication using local and common sema...