Richard Rouse

Person

San Francisco, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of making recessed source drains to reduce fringing capacitance
- Patent number 6,531,347
- Issue date Mar 11, 2003
- Advanced Micro Devices, Inc.
- Carl R. Huster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-uniform channel profile via enhanced diffusion
- Patent number 6,503,801
- Issue date Jan 7, 2003
- Advanced Micro Devices, Inc.
- Richard P. Rouse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxygen implantation for reduction of junction capacitance in MOS tr...
- Patent number 6,475,868
- Issue date Nov 5, 2002
- Advanced Micro Devices, Inc.
- Ming Yin Hao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Indium retrograde channel doping for improved gate oxide reliability
- Patent number 6,372,582
- Issue date Apr 16, 2002
- Advanced Micro Devices, Inc.
- Richard P. Rouse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual spacer method of forming CMOS transistors with substantially t...
- Patent number 6,306,702
- Issue date Oct 23, 2001
- Advanced Micro Devices, Inc.
- Ming Yin Hao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing asymmetric channel transistor
- Patent number 6,242,329
- Issue date Jun 5, 2001
- Advanced Micro Devices, Inc.
- Carl Robert Huster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned damascene gate with contact formation
- Patent number 6,225,170
- Issue date May 1, 2001
- Advanced Micro Devices, Inc.
- Effiong Ibok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a MOS device with self-compensating V.sub.T -imp...
- Patent number 6,080,630
- Issue date Jun 27, 2000
- Advanced Micro Devices, Inc.
- Ognjen Milic-Strkalj
- H01 - BASIC ELECTRIC ELEMENTS

Richard Rouse

Person

Patents Grantslast 30 patents

Method of making recessed source drains to reduce fringing capacitance

Non-uniform channel profile via enhanced diffusion

Oxygen implantation for reduction of junction capacitance in MOS tr...

Indium retrograde channel doping for improved gate oxide reliability

Dual spacer method of forming CMOS transistors with substantially t...

Method for manufacturing asymmetric channel transistor

Self-aligned damascene gate with contact formation

Method for forming a MOS device with self-compensating V.sub.T -imp...