Richard Walke

Person

Edinburgh, GB

People

Patents Grantslast 30 patents

Information Patent Grant
Data processing engine arrangement in a device
- Patent number 11,972,132
- Issue date Apr 30, 2024
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared multi-port memory from single port
- Patent number 11,721,373
- Issue date Aug 8, 2023
- Xilinx, Inc.
- Richard Lewis Walke
- G11 - INFORMATION STORAGE
Information Patent Grant
Data processing engine arrangement in a device
- Patent number 11,573,726
- Issue date Feb 7, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared multi-port memory from single port
- Patent number 11,348,624
- Issue date May 31, 2022
- Xilinx, Inc.
- Richard Lewis Walke
- G11 - INFORMATION STORAGE
Information Patent Grant
User-programmable LDPC decoder
- Patent number 11,108,410
- Issue date Aug 31, 2021
- Xilinx, Inc.
- Richard L. Walke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for determining bit types for polar encoding and...
- Patent number 11,082,067
- Issue date Aug 3, 2021
- Xilinx, Inc.
- Ming Ruan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sub-matrix reduction for quasi-cyclic LDPC codes
- Patent number 11,075,650
- Issue date Jul 27, 2021
- Xilinx, Inc.
- Andrew Dow
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data selection network for a data processing engine in an integrate...
- Patent number 11,061,673
- Issue date Jul 13, 2021
- Xilinx, Inc.
- Baris Ozgul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascade streaming between data processing engines in an array
- Patent number 11,016,822
- Issue date May 25, 2021
- Xilinx, Inc.
- Goran H. K. Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming interconnect architecture for data processing engine array
- Patent number 10,990,552
- Issue date Apr 27, 2021
- Xilinx, Inc.
- Goran Hk Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine arrangement in a device
- Patent number 10,866,753
- Issue date Dec 15, 2020
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-density parity check decoder using encoded no-operation instruc...
- Patent number 10,833,704
- Issue date Nov 10, 2020
- Xilinx, Inc.
- Richard L. Walke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-density parity-check (LDPC) encode using an LDPC decoder
- Patent number 10,797,727
- Issue date Oct 6, 2020
- Xilinx, Inc.
- Richard L. Walke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device with data processing engine array
- Patent number 10,747,690
- Issue date Aug 18, 2020
- Xilinx, Inc.
- Goran H K Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient method for packing low-density parity-check (LDPC) decode...
- Patent number 10,727,869
- Issue date Jul 28, 2020
- Xilinx, Inc.
- Richard L. Walke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Software defined modem
- Patent number 10,673,564
- Issue date Jun 2, 2020
- Xilinx, Inc.
- Richard L. Walke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interleaved data block processing in low-density parity-check (LDPC...
- Patent number 10,644,725
- Issue date May 5, 2020
- Xilinx, Inc.
- Richard L. Walke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for decoding quasi-cyclic (QC) low-density pari...
- Patent number 10,484,012
- Issue date Nov 19, 2019
- Xilinx, Inc.
- Nihat E. Tunali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Log-likelihood ratio processing for linear block code decoding
- Patent number 10,484,021
- Issue date Nov 19, 2019
- Xilinx, Inc.
- Gordon I. Old
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplier circuits configurable for real or complex operation
- Patent number 9,778,905
- Issue date Oct 3, 2017
- Xilinx, Inc.
- Richard L. Walke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital signal processing block
- Patent number 9,081,634
- Issue date Jul 14, 2015
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for and method of providing a floating-point adder
- Patent number 8,463,835
- Issue date Jun 11, 2013
- Xilinx, Inc.
- Richard Walke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining efficient buffering for multi-dimensional datastream ap...
- Patent number 8,365,109
- Issue date Jan 29, 2013
- Xilinx, Inc.
- Thomas P. Perry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital signal processing engine
- Patent number 8,250,342
- Issue date Aug 21, 2012
- Xilinx, Inc.
- Igor Kostarnov
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
- Publication number 20230131698
- Publication date Apr 27, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED MULTI-PORT MEMORY FROM SINGLE PORT
- Publication number 20230023866
- Publication date Jan 26, 2023
- Xilinx, Inc.
- Richard Lewis WALKE
- G11 - INFORMATION STORAGE
Information Patent Application
DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
- Publication number 20190303033
- Publication date Oct 3, 2019
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE WITH DATA PROCESSING ENGINE ARRAY
- Publication number 20190303311
- Publication date Oct 3, 2019
- Xilinx, Inc.
- Goran HK Bilski
- G06 - COMPUTING CALCULATING COUNTING

Richard Walke

Person

Patents Grantslast 30 patents

Data processing engine arrangement in a device

Shared multi-port memory from single port

Data processing engine arrangement in a device

Shared multi-port memory from single port

User-programmable LDPC decoder

System and method for determining bit types for polar encoding and...

Sub-matrix reduction for quasi-cyclic LDPC codes

Data selection network for a data processing engine in an integrate...

Cascade streaming between data processing engines in an array

Streaming interconnect architecture for data processing engine array

Data processing engine arrangement in a device

Low-density parity check decoder using encoded no-operation instruc...

Low-density parity-check (LDPC) encode using an LDPC decoder

Device with data processing engine array

Efficient method for packing low-density parity-check (LDPC) decode...

Software defined modem

Interleaved data block processing in low-density parity-check (LDPC...

Systems and methods for decoding quasi-cyclic (QC) low-density pari...

Log-likelihood ratio processing for linear block code decoding

Multiplier circuits configurable for real or complex operation

Digital signal processing block

Circuit for and method of providing a floating-point adder

Determining efficient buffering for multi-dimensional datastream ap...

Digital signal processing engine

Patents Applicationslast 30 patents

DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE

SHARED MULTI-PORT MEMORY FROM SINGLE PORT

DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE

DEVICE WITH DATA PROCESSING ENGINE ARRAY