Richard Win Thaik

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hazard prediction for a group of memory access instructions using a...
- Patent number 11,093,401
- Issue date Aug 17, 2021
- Ampere Computing LLC
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Allocation of load instruction(s) to a queue buffer in a processor...
- Patent number 9,880,849
- Issue date Jan 30, 2018
- MACOM CONNECTIVITY SOLUTIONS, LLC
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symbolic renaming optimization of a trace
- Patent number 8,499,293
- Issue date Jul 30, 2013
- Oracle America, Inc.
- Matthew William Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trace unit
- Patent number 8,037,285
- Issue date Oct 11, 2011
- Oracle America, Inc.
- Richard Win Thaik
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method for ensuring coherency in trace execution
- Patent number 8,032,710
- Issue date Oct 4, 2011
- Oracle America, Inc.
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for utilizing a common structure for trace verifi...
- Patent number 8,015,359
- Issue date Sep 6, 2011
- Oracle America, Inc.
- John Gregory Favor
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Trace unit with a decoder, a basic-block cache, a multi-block cache...
- Patent number 7,987,342
- Issue date Jul 26, 2011
- Oracle America, Inc.
- Richard Win Thaik
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Concurrent vs. low power branch prediction
- Patent number 7,966,479
- Issue date Jun 21, 2011
- Oracle America, Inc.
- Richard Win Thaik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trace unit with an op path from a decoder (bypass mode) and from a...
- Patent number 7,953,961
- Issue date May 31, 2011
- Oracle America, Inc.
- Richard Win Thaik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction cache, decoder circuit, basic block cache circuit and m...
- Patent number 7,953,933
- Issue date May 31, 2011
- Oracle America, Inc.
- Richard Win Thaik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trace unit with a trace builder
- Patent number 7,949,854
- Issue date May 24, 2011
- Oracle America, Inc.
- Richard Win Thaik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for promoting traces in an instruction processing...
- Patent number 7,941,607
- Issue date May 10, 2011
- Oracle America, Inc.
- Richard Thaik
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Emit vector optimization of a trace
- Patent number 7,937,564
- Issue date May 3, 2011
- Oracle America, Inc.
- Matthew William Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Abort prioritization in a trace-based processor
- Patent number 7,870,369
- Issue date Jan 11, 2011
- Oracle America, Inc.
- Christopher Patrick Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flag optimization of a trace
- Patent number 7,849,292
- Issue date Dec 7, 2010
- Oracle America, Inc.
- Matthew William Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Promoting and appending traces in an instruction processing circuit...
- Patent number 7,814,298
- Issue date Oct 12, 2010
- Oracle America, Inc.
- Richard Thaik
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Graceful degradation in a trace-based processor
- Patent number 7,783,863
- Issue date Aug 24, 2010
- Oracle America, Inc.
- Christopher Patrick Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining memory coherency with a trace cache
- Patent number 7,747,822
- Issue date Jun 29, 2010
- Oracle America Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software hint to specify the preferred branch prediction to use for...
- Patent number 7,673,122
- Issue date Mar 2, 2010
- Sun Microsystems, Inc.
- Seungyoon Peter Song
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HAZARD PREDICTION FOR A GROUP OF MEMORY ACCESS INSTRUCTIONS USING A...
- Publication number 20150324203
- Publication date Nov 12, 2015
- Applied Micro Circuits Corporation
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALLOCATION OF LOAD INSTRUCTION(S) TO A QUEUE BUFFER IN A PROCESSOR...
- Publication number 20150160945
- Publication date Jun 11, 2015
- Applied Micro Circuits Corporation
- Matthew Ashcraft
- G06 - COMPUTING CALCULATING COUNTING

Richard Win Thaik

Person

Patents Grantslast 30 patents

Hazard prediction for a group of memory access instructions using a...

Allocation of load instruction(s) to a queue buffer in a processor...

Symbolic renaming optimization of a trace

Trace unit

System and method for ensuring coherency in trace execution

Method and system for utilizing a common structure for trace verifi...

Trace unit with a decoder, a basic-block cache, a multi-block cache...

Concurrent vs. low power branch prediction

Trace unit with an op path from a decoder (bypass mode) and from a...

Instruction cache, decoder circuit, basic block cache circuit and m...

Trace unit with a trace builder

Method and system for promoting traces in an instruction processing...

Emit vector optimization of a trace

Abort prioritization in a trace-based processor

Flag optimization of a trace

Promoting and appending traces in an instruction processing circuit...

Graceful degradation in a trace-based processor

Maintaining memory coherency with a trace cache

Software hint to specify the preferred branch prediction to use for...

Patents Applicationslast 30 patents

HAZARD PREDICTION FOR A GROUP OF MEMORY ACCESS INSTRUCTIONS USING A...

ALLOCATION OF LOAD INSTRUCTION(S) TO A QUEUE BUFFER IN A PROCESSOR...