Rinus T. P. Lee

Person

Ballston Spa, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Single diffusion breaks including stacked dielectric layers
- Patent number 11,545,574
- Issue date Jan 3, 2023
- GLOBALFOUNDRIES U.S. INC.
- Haiting Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric source drain structures
- Patent number 11,362,178
- Issue date Jun 14, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Jiehui Shu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices with low resistance gate structures
- Patent number 11,145,716
- Issue date Oct 12, 2021
- GLOBALFOUNDRIES U.S. INC.
- Rinus Tek Po Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple threshold voltage devices
- Patent number 11,094,598
- Issue date Aug 17, 2021
- GLOBALFOUNDRIES U.S. INC.
- Bharat V. Krishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mask-free methods of forming structures in a semiconductor device
- Patent number 11,004,953
- Issue date May 11, 2021
- GLOBALFOUNDRIES U.S. INC.
- Rinus Tek Po Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mask-free methods of forming structures in a semiconductor device
- Patent number 10,896,853
- Issue date Jan 19, 2021
- GLOBALFOUNDRIES Inc.
- Jiehui Shu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory array with buried bitlines below vertical field effect trans...
- Patent number 10,418,365
- Issue date Sep 17, 2019
- GLOBALFOUNDRIES Inc.
- Hui Zang
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Microwave annealing of flowable oxides with trap layers
- Patent number 10,211,045
- Issue date Feb 19, 2019
- GLOBALFOUNDRIES Inc.
- Rishikesh Krishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods, apparatus and system for vertical finFET device with reduc...
- Patent number 10,204,904
- Issue date Feb 12, 2019
- GLOBALFOUNDRIES Inc.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFETs with strained channels and reduced on state resistance
- Patent number 10,134,876
- Issue date Nov 20, 2018
- GLOBALFOUNDRIES Inc.
- Bharat V. Krishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory array with buried bitlines below vertical field effect trans...
- Patent number 10,134,739
- Issue date Nov 20, 2018
- GLOBALFOUNDRIES Inc.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure including two-dimensional and three-dimensi...
- Patent number 10,121,706
- Issue date Nov 6, 2018
- GLOBALFOUNDRIES Inc.
- Rinus T. P. Lee
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SINGLE DIFFUSION BREAKS INCLUDING STACKED DIELECTRIC LAYERS
- Publication number 20220052193
- Publication date Feb 17, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Haiting Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYMMETRIC SOURCE DRAIN STRUCTURES
- Publication number 20210143254
- Publication date May 13, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Jiehui SHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE THRESHOLD VOLTAGE DEVICES
- Publication number 20210013109
- Publication date Jan 14, 2021
- GLOBALFOUNDRIES INC.
- Bharat V. KRISHNAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MASK-FREE METHODS OF FORMING STRUCTURES IN A SEMICONDUCTOR DEVICE
- Publication number 20200411664
- Publication date Dec 31, 2020
- GLOBALFOUNDRIES INC.
- RINUS TEK PO LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MASK-FREE METHODS OF FORMING STRUCTURES IN A SEMICONDUCTOR DEVICE
- Publication number 20200343142
- Publication date Oct 29, 2020
- GLOBALFOUNDRIES INC.
- JIEHUI SHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING A BARRIER LAYER MADE OF TWO DIMENSIONAL...
- Publication number 20200312775
- Publication date Oct 1, 2020
- GLOBALFOUNDRIES INC.
- RINUS TEK PO LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY ARRAY WITH BURIED BITLINES BELOW VERTICAL FIELD EFFECT TRANS...
- Publication number 20190035791
- Publication date Jan 31, 2019
- GLOBALFOUNDRIES INC.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS, APPARATUS AND SYSTEM FOR VERTICAL FINFET DEVICE WITH REDUC...
- Publication number 20180331097
- Publication date Nov 15, 2018
- GLOBALFOUNDRIES INC.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFETs WITH STRAINED CHANNELS AND REDUCED ON STATE RESISTANCE
- Publication number 20180286982
- Publication date Oct 4, 2018
- GLOBALFOUNDRIES INC.
- Bharat V. KRISHNAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING TWO-DIMENSIONAL AND THREE-DIMENSI...
- Publication number 20180151449
- Publication date May 31, 2018
- GLOBALFOUNDRIES INC.
- Rinus T. P. Lee
- H01 - BASIC ELECTRIC ELEMENTS

Rinus T. P. Lee

Person

Patents Grantslast 30 patents

Single diffusion breaks including stacked dielectric layers

Asymmetric source drain structures

Semiconductor devices with low resistance gate structures

Multiple threshold voltage devices

Mask-free methods of forming structures in a semiconductor device

Mask-free methods of forming structures in a semiconductor device

Memory array with buried bitlines below vertical field effect trans...

Microwave annealing of flowable oxides with trap layers

Methods, apparatus and system for vertical finFET device with reduc...

FinFETs with strained channels and reduced on state resistance

Memory array with buried bitlines below vertical field effect trans...

Semiconductor structure including two-dimensional and three-dimensi...

Patents Applicationslast 30 patents

SINGLE DIFFUSION BREAKS INCLUDING STACKED DIELECTRIC LAYERS

ASYMMETRIC SOURCE DRAIN STRUCTURES

MULTIPLE THRESHOLD VOLTAGE DEVICES

MASK-FREE METHODS OF FORMING STRUCTURES IN A SEMICONDUCTOR DEVICE

MASK-FREE METHODS OF FORMING STRUCTURES IN A SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE HAVING A BARRIER LAYER MADE OF TWO DIMENSIONAL...

MEMORY ARRAY WITH BURIED BITLINES BELOW VERTICAL FIELD EFFECT TRANS...

METHODS, APPARATUS AND SYSTEM FOR VERTICAL FINFET DEVICE WITH REDUC...

FINFETs WITH STRAINED CHANNELS AND REDUCED ON STATE RESISTANCE

SEMICONDUCTOR STRUCTURE INCLUDING TWO-DIMENSIONAL AND THREE-DIMENSI...