Rishi Bhooshan

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Greater Noida, IN

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Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with timing correction circuitry
- Patent number 12,123,911
- Issue date Oct 22, 2024
- NXP USA, INC.
- Shilpa Gupta
- G01 - MEASURING TESTING
Information Patent Grant
Plated pillar dies having integrated electromagnetic shield layers
- Patent number 11,694,970
- Issue date Jul 4, 2023
- NXP B.V.
- Douglas Michael Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for reducing mutual coupling for noise reduction...
- Patent number 11,488,904
- Issue date Nov 1, 2022
- NXP B.V.
- Ajay Kumar Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated input/output pad and analog multiplexer architecture
- Patent number 11,449,657
- Issue date Sep 20, 2022
- NXP USA, INC.
- Wenzhong Zhang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE HAVING ELECTROMAGNETIC INTERFERENCE (EMI) SENS...
- Publication number 20250052798
- Publication date Feb 13, 2025
- NXP B.V.
- Shilpa Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH TIMING CORRECTION CIRCUITRY
- Publication number 20240345163
- Publication date Oct 17, 2024
- NXP USA, Inc.
- Shilpa Gupta
- G01 - MEASURING TESTING
Information Patent Application
PLATED PILLAR DIES HAVING INTEGRATED ELECTROMAGNETIC SHIELD LAYERS
- Publication number 20220302042
- Publication date Sep 22, 2022
- NXP B.V.
- Douglas Michael Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR REDUCING MUTUAL COUPLING FOR NOISE REDUCTION...
- Publication number 20220208672
- Publication date Jun 30, 2022
- NXP B.V.
- Ajay Kumar Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED INPUT/OUTPUT PAD AND ANALOG MULTIPLEXER ARCHITECTURE
- Publication number 20220188499
- Publication date Jun 16, 2022
- NXP USA, Inc.
- Wenzhong Zhang
- G06 - COMPUTING CALCULATING COUNTING