Ritesh JHAVERI

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Advanced etching technologies for straight, tall and uniform fins a...
- Patent number 12,131,912
- Issue date Oct 29, 2024
- Intel Corporation
- Muralidhar S. Ambati
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arsenic-doped epitaxial source/drain regions for NMOS
- Patent number 12,094,881
- Issue date Sep 17, 2024
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced etching technologies for straight, tall and uniform fins a...
- Patent number 11,875,999
- Issue date Jan 16, 2024
- Intel Corporation
- Muralidhar S. Ambati
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arsenic-doped epitaxial, source/drain regions for NMOS
- Patent number 11,610,889
- Issue date Mar 21, 2023
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced etching technologies for straight, tall and uniform fins a...
- Patent number 11,417,531
- Issue date Aug 16, 2022
- Intel Corporation
- Muralidhar S. Ambati
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors employing non-selective deposition of source/drain mate...
- Patent number 11,101,268
- Issue date Aug 24, 2021
- Intel Corporation
- Karthik Jambunathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for increasing channel region tensile strain in n-MOS de...
- Patent number 11,011,620
- Issue date May 18, 2021
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced etching technologies for straight, tall and uniform fins a...
- Patent number 10,950,453
- Issue date Mar 16, 2021
- Intel Corporation
- Muralidhar S. Ambati
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced etching technologies for straight, tall and uniform fins a...
- Patent number 10,643,855
- Issue date May 5, 2020
- Intel Corporation
- Muralidhar S. Ambati
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced etching technologies for straight, tall and uniform fins a...
- Patent number 10,204,794
- Issue date Feb 12, 2019
- Intel Corporation
- Muralidhar S. Ambati
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for trench isolation using flowable dielectric materials
- Patent number 10,147,634
- Issue date Dec 4, 2018
- Intel Corporation
- Ritesh Jhaveri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin structure having hard mask etch stop layers underneath gate sid...
- Patent number 9,923,054
- Issue date Mar 20, 2018
- Intel Corporation
- Ritesh Jhaveri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for trench isolation using flowable dielectric materials
- Patent number 9,406,547
- Issue date Aug 2, 2016
- Intel Corporation
- Ritesh Jhaveri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a semiconductor device with tall fins and using h...
- Patent number 9,048,260
- Issue date Jun 2, 2015
- Intel Corporation
- Ritesh Jhaveri
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...
- Publication number 20240120206
- Publication date Apr 11, 2024
- Intel Corporation
- Muralidhar S. AMBATI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARSENIC-DOPED EPITAXIAL SOURCE/DRAIN REGIONS FOR NMOS
- Publication number 20230197729
- Publication date Jun 22, 2023
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...
- Publication number 20220344165
- Publication date Oct 27, 2022
- Intel Corporation
- Muralidhar S. AMBATI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...
- Publication number 20210183658
- Publication date Jun 17, 2021
- Intel Corporation
- Muralidhar S. AMBATI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...
- Publication number 20200227266
- Publication date Jul 16, 2020
- Intel Corporation
- Muralidhar S. AMBATI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARSENIC-DOPED EPITAXIAL SOURCE/DRAIN REGIONS FOR NMOS
- Publication number 20200105754
- Publication date Apr 2, 2020
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTORS EMPLOYING NON-SELECTIVE DEPOSITION OF SOURCE/DRAIN MATE...
- Publication number 20190355721
- Publication date Nov 21, 2019
- Intel Corporation
- KARTHIK JAMBUNATHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR INCREASING CHANNEL REGION TENSILE STRAIN IN N-MOS DE...
- Publication number 20190207015
- Publication date Jul 4, 2019
- Intel Corporation
- RISHABH MEHANDRU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...
- Publication number 20190131138
- Publication date May 2, 2019
- Intel Corporation
- Muralidhar S. AMBATI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RESISTANCE REDUCTION UNDER TRANSISTOR SPACERS
- Publication number 20180240874
- Publication date Aug 23, 2018
- Intel Corporation
- CORY E. WEBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR TRENCH ISOLATION USING FLOWABLE DIELECTRIC MATERIALS
- Publication number 20160343609
- Publication date Nov 24, 2016
- Intel Corporation
- Ritesh JHAVERI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...
- Publication number 20160300725
- Publication date Oct 13, 2016
- Intel Corporation
- Muralidhar S. AMBATI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH TALL FINS AND USING H...
- Publication number 20150287779
- Publication date Oct 8, 2015
- Intel Corporation
- Ritesh Jhaveri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR TRENCH ISOLATION USING FLOWABLE DIELECTRIC MATERIALS
- Publication number 20150179501
- Publication date Jun 25, 2015
- Ritesh Jhaveri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HARD MASK ETCH STOP FOR TALL FINS
- Publication number 20140191300
- Publication date Jul 10, 2014
- Ritesh Jhaveri
- H01 - BASIC ELECTRIC ELEMENTS

Ritesh JHAVERI

Person

Patents Grantslast 30 patents

Advanced etching technologies for straight, tall and uniform fins a...

Arsenic-doped epitaxial source/drain regions for NMOS

Advanced etching technologies for straight, tall and uniform fins a...

Arsenic-doped epitaxial, source/drain regions for NMOS

Advanced etching technologies for straight, tall and uniform fins a...

Transistors employing non-selective deposition of source/drain mate...

Techniques for increasing channel region tensile strain in n-MOS de...

Advanced etching technologies for straight, tall and uniform fins a...

Advanced etching technologies for straight, tall and uniform fins a...

Advanced etching technologies for straight, tall and uniform fins a...

Techniques for trench isolation using flowable dielectric materials

Fin structure having hard mask etch stop layers underneath gate sid...

Techniques for trench isolation using flowable dielectric materials

Method of forming a semiconductor device with tall fins and using h...

Patents Applicationslast 30 patents

ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...

ARSENIC-DOPED EPITAXIAL SOURCE/DRAIN REGIONS FOR NMOS

ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...

ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...

ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...

ARSENIC-DOPED EPITAXIAL SOURCE/DRAIN REGIONS FOR NMOS

TRANSISTORS EMPLOYING NON-SELECTIVE DEPOSITION OF SOURCE/DRAIN MATE...

TECHNIQUES FOR INCREASING CHANNEL REGION TENSILE STRAIN IN N-MOS DE...

ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...

RESISTANCE REDUCTION UNDER TRANSISTOR SPACERS

TECHNIQUES FOR TRENCH ISOLATION USING FLOWABLE DIELECTRIC MATERIALS

ADVANCED ETCHING TECHNOLOGIES FOR STRAIGHT, TALL AND UNIFORM FINS A...

METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH TALL FINS AND USING H...

TECHNIQUES FOR TRENCH ISOLATION USING FLOWABLE DIELECTRIC MATERIALS

HARD MASK ETCH STOP FOR TALL FINS