Ritesh P. Turakhia

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Portland, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Method for generating test patterns for small delay defects
- Patent number 8,352,818
- Issue date Jan 8, 2013
- LSI Corporation
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Methods of screening ASIC defects using independent component analy...
- Patent number 7,171,638
- Issue date Jan 30, 2007
- LSI Logic Corporation
- Ritesh P. Turakhia
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR GENERATING TEST PATTERNS FOR SMALL DELAY DEFECTS
- Publication number 20100153795
- Publication date Jun 17, 2010
- LSI Corporation
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Application
Method of screening ASIC defects using independent component analys...
- Publication number 20060085771
- Publication date Apr 20, 2006
- LSI Logic Corporation
- Ritesh P. Turakhia
- G01 - MEASURING TESTING