Ritwik Chatterjee

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method to form a via
- Patent number 8,586,474
- Issue date Nov 19, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Ritwik Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3-D semiconductor die structure with containing feature and method
- Patent number 8,581,383
- Issue date Nov 12, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming interconnects for 3-D applications
- Patent number 8,003,517
- Issue date Aug 23, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Varughese Mathew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming a 3-D semiconductor die structure with an intermetallic for...
- Patent number 7,993,971
- Issue date Aug 9, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Ritwik Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form a via
- Patent number 7,932,175
- Issue date Apr 26, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Ritwik Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3-D semiconductor die structure with containing feature and method
- Patent number 7,811,932
- Issue date Oct 12, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micropad formation for a semiconductor
- Patent number 7,807,572
- Issue date Oct 5, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Varughese Mathew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a through silicon via layout
- Patent number 7,799,678
- Issue date Sep 21, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Thomas J. Kropewnicki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual plasma treatment barrier film to reduce low-k damage
- Patent number 7,763,538
- Issue date Jul 27, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Michael D. Turner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor interconnect having adjacent reservoir for bonding an...
- Patent number 7,579,258
- Issue date Aug 25, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Ritwik Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micropad for bonding and a method therefor
- Patent number 7,572,723
- Issue date Aug 11, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Varughese Mathew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a semiconductor device having a diffusion barrier...
- Patent number 7,422,979
- Issue date Sep 9, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Lynne M. Michaelson
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD TO FORM A VIA
- Publication number 20110151663
- Publication date Jun 23, 2011
- Freescale Semiconductor Inc.
- Ritwik Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD
- Publication number 20100327440
- Publication date Dec 30, 2010
- FREESCALE SEMICONDUCTOR, INC.
- SCOTT K. POZDER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A THROUGH SILICON VIA LAYOUT
- Publication number 20090191708
- Publication date Jul 30, 2009
- Thomas J. Kropewnicki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROPAD FORMATION FOR A SEMICONDUCTOR
- Publication number 20090176366
- Publication date Jul 9, 2009
- Varughese Mathew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING A 3-D SEMICONDUCTOR DIE STRUCTURE WITH AN INTERMETALLIC FOR...
- Publication number 20090170246
- Publication date Jul 2, 2009
- Ritwik Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD
- Publication number 20090166888
- Publication date Jul 2, 2009
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming interconnects for 3-D applications
- Publication number 20080299762
- Publication date Dec 4, 2008
- Freescale Semiconductor, Inc.
- Varughese Mathew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to form a via
- Publication number 20080299759
- Publication date Dec 4, 2008
- Freescale Semiconductor, Inc.
- Ritwik Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A THROUGH-SUBSTRATE VIA
- Publication number 20080113505
- Publication date May 15, 2008
- Terry G. Sparks
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROPAD FOR BONDING AND A METHOD THEREFOR
- Publication number 20080099799
- Publication date May 1, 2008
- Varughese Mathew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor interconnect having adjacent reservoir for bonding an...
- Publication number 20070170584
- Publication date Jul 26, 2007
- Ritwik Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual plasma treatment barrier film to reduce low-k damage
- Publication number 20070161229
- Publication date Jul 12, 2007
- Freescale Semiconductor, Inc.
- Michael D. Turner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a semiconductor device having a diffusion barrier...
- Publication number 20060202339
- Publication date Sep 14, 2006
- Lynne M. Michaelson
- H01 - BASIC ELECTRIC ELEMENTS

Ritwik Chatterjee

Person

Patents Grantslast 30 patents

Method to form a via

3-D semiconductor die structure with containing feature and method

Method for forming interconnects for 3-D applications

Forming a 3-D semiconductor die structure with an intermetallic for...

Method to form a via

3-D semiconductor die structure with containing feature and method

Micropad formation for a semiconductor

Method for forming a through silicon via layout

Dual plasma treatment barrier film to reduce low-k damage

Semiconductor interconnect having adjacent reservoir for bonding an...

Micropad for bonding and a method therefor

Method of forming a semiconductor device having a diffusion barrier...

Patents Applicationslast 30 patents

METHOD TO FORM A VIA

3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD

METHOD FOR FORMING A THROUGH SILICON VIA LAYOUT

MICROPAD FORMATION FOR A SEMICONDUCTOR

FORMING A 3-D SEMICONDUCTOR DIE STRUCTURE WITH AN INTERMETALLIC FOR...

3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD

Method for forming interconnects for 3-D applications

Method to form a via

METHOD OF FORMING A THROUGH-SUBSTRATE VIA

MICROPAD FOR BONDING AND A METHOD THEREFOR

Semiconductor interconnect having adjacent reservoir for bonding an...

Dual plasma treatment barrier film to reduce low-k damage

Method of forming a semiconductor device having a diffusion barrier...