Riyas Noorudeen Remla

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Patents Grantslast 30 patents

Information Patent Grant
Configurable testing of semiconductor devices
- Patent number 11,681,844
- Issue date Jun 20, 2023
- Xilinx, Inc.
- Riyas Noorudeen Remla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serial lane-to-lane skew reduction
- Patent number 11,314,277
- Issue date Apr 26, 2022
- Xilinx, Inc.
- Riyas Noorudeen Remla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for dynamic clock skew compensation
- Patent number 10,924,096
- Issue date Feb 16, 2021
- Xilinx, Inc.
- Gourav Modi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency data transfer technique for mesochronous divided clocks
- Patent number 10,623,174
- Issue date Apr 14, 2020
- Xilinx, Inc.
- Riyas Noorudeen Remla
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable system and method for debugging a circuit
- Patent number 10,161,999
- Issue date Dec 25, 2018
- Xilinx, Inc.
- Heera Nand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for and method of measuring latency in an integrated circuit
- Patent number 10,033,523
- Issue date Jul 24, 2018
- Xilinx, Inc.
- Riyas Noorudeen Remla
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Built-in integrated circuit debug design
- Patent number 9,083,347
- Issue date Jul 14, 2015
- Xilinx, Inc.
- Riyas Noorudeen Remla
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
LOW LATENCY PHASE ALIGNMENT FOR PARALLEL DATA PATHS
- Publication number 20240333270
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Riyas Noorudeen REMLA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DETERMINISTIC RESET MECHANISM FOR ASYNCHRONOUS GEARBOX FIFOS FOR PR...
- Publication number 20240329924
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Riyas Noorudeen REMLA
- G06 - COMPUTING CALCULATING COUNTING