Robert B. Eisenhuth

Person

Boulder, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Read threshold adjustment techniques for non-binary memory cells
- Patent number 11,934,688
- Issue date Mar 19, 2024
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read threshold adjustment techniques for memory
- Patent number 11,854,641
- Issue date Dec 26, 2023
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G11 - INFORMATION STORAGE
Information Patent Grant
Advanced bitwise operations and apparatus in a multi-level system w...
- Patent number 11,804,856
- Issue date Oct 31, 2023
- Micron Technology, Inc.
- Robert B Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read threshold adjustment techniques for non-binary memory cells
- Patent number 11,494,114
- Issue date Nov 8, 2022
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell state in a valley between adjacent data states
- Patent number 11,450,382
- Issue date Sep 20, 2022
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read threshold adjustment techniques for memory
- Patent number 11,443,828
- Issue date Sep 13, 2022
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient scrambling and encoding for copyback procedures using pre...
- Patent number 11,416,393
- Issue date Aug 16, 2022
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Advanced bitwise operations and apparatus in a multi-level system w...
- Patent number 11,336,303
- Issue date May 17, 2022
- Micron Technology, Inc.
- Robert B Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient scrambling and encoding for copyback procedures using pre...
- Patent number 10,997,070
- Issue date May 4, 2021
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient scrambling and encoding for copyback procedures in a memo...
- Patent number 10,923,211
- Issue date Feb 16, 2021
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell state in a valley between adjacent data states
- Patent number 10,811,090
- Issue date Oct 20, 2020
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Advanced bitwise operations and apparatus in a multi-level system w...
- Patent number 10,740,173
- Issue date Aug 11, 2020
- Micron Technology, Inc.
- Robert B Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Progressive effort decoder architecture
- Patent number 10,498,367
- Issue date Dec 3, 2019
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bitwise operations and apparatus in a multi-level system
- Patent number 10,355,815
- Issue date Jul 16, 2019
- Micron Technology, Inc.
- Bruce A. Liikanen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining whether a memory cell state is in a valley between adja...
- Patent number 9,990,988
- Issue date Jun 5, 2018
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G11 - INFORMATION STORAGE
Information Patent Grant
Progressive effort decoder architecture
- Patent number 9,654,144
- Issue date May 16, 2017
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Advanced bitwise operations and apparatus in a multi-level system w...
- Patent number 9,411,675
- Issue date Aug 9, 2016
- Micron Technology, Inc.
- Robert B Eisenhuth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bitwise operations and apparatus in a multi-level system
- Patent number 9,374,343
- Issue date Jun 21, 2016
- Micron Technology, Inc.
- Bruce A. Liikanen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Determining whether a memory cell state is in a valley between adja...
- Patent number 9,064,575
- Issue date Jun 23, 2015
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G11 - INFORMATION STORAGE
Information Patent Grant
Advanced converters for memory cell sensing and methods
- Patent number 8,782,474
- Issue date Jul 15, 2014
- Micron Technology, Inc.
- Larry J. Koudele
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitwise operations and apparatus in a multi-level system
- Patent number 8,627,165
- Issue date Jan 7, 2014
- Micron Technology, Inc.
- Bruce A. Liikanen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Advanced bitwise operations and apparatus in a multi-level system w...
- Patent number 8,615,703
- Issue date Dec 24, 2013
- Micron Technology, Inc.
- Robert B Eisenhuth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Advanced converters for memory cell sensing and methods
- Patent number 8,522,087
- Issue date Aug 27, 2013
- Micron Technology, Inc.
- Larry J. Koudele
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital full-duplex transceiver
- Patent number 5,436,887
- Issue date Jul 25, 1995
- Storage Technology Corporation
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
READ THRESHOLD ADJUSTMENT TECHNIQUES FOR NON-BINARY MEMORY CELLS
- Publication number 20230124024
- Publication date Apr 20, 2023
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ THRESHOLD ADJUSTMENT TECHNIQUES FOR MEMORY
- Publication number 20230030713
- Publication date Feb 2, 2023
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G11 - INFORMATION STORAGE
Information Patent Application
READ THRESHOLD ADJUSTMENT TECHNIQUES FOR NON-BINARY MEMORY CELLS
- Publication number 20220365704
- Publication date Nov 17, 2022
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM W...
- Publication number 20220209795
- Publication date Jun 30, 2022
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT SCRAMBLING AND ENCODING FOR COPYBACK PROCEDURES USING PRE...
- Publication number 20210216449
- Publication date Jul 15, 2021
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES
- Publication number 20210035631
- Publication date Feb 4, 2021
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES
- Publication number 20180268896
- Publication date Sep 20, 2018
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRESSIVE EFFORT DECODER ARCHITECTURE
- Publication number 20170222663
- Publication date Aug 3, 2017
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM W...
- Publication number 20160314039
- Publication date Oct 27, 2016
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM
- Publication number 20160269147
- Publication date Sep 15, 2016
- Micron Technology, Inc.
- Bruce A. Liikanen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRESSIVE EFFORT DECODER ARCHITECTURE
- Publication number 20160094247
- Publication date Mar 31, 2016
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DETERMINING WHETHER A MEMORY CELL STATE IS IN A VALLEY BETWEEN ADJA...
- Publication number 20150310911
- Publication date Oct 29, 2015
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM
- Publication number 20140093076
- Publication date Apr 3, 2014
- Micron Technology, Inc.
- Bruce A. Liikanen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM W...
- Publication number 20140082454
- Publication date Mar 20, 2014
- Micron Technology, Inc.
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES
- Publication number 20140036589
- Publication date Feb 6, 2014
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADVANCED CONVERTERS FOR MEMORY CELL SENSING AND METHODS
- Publication number 20130332793
- Publication date Dec 12, 2013
- Micron Technology, Inc.
- Larry J. Koudele
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADVANCED CONVERTERS FOR MEMORY CELL SENSING AND METHODS
- Publication number 20120194221
- Publication date Aug 2, 2012
- Larry J. Koudele
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Advanced Bitwise Operations and Apparatus in a Multi-Level System w...
- Publication number 20110302475
- Publication date Dec 8, 2011
- Robert B. Eisenhuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bitwise Operations and Apparatus in a Multi-Level System
- Publication number 20090241006
- Publication date Sep 24, 2009
- Bruce A. Liikanen
- G06 - COMPUTING CALCULATING COUNTING

Robert B. Eisenhuth

Person

Patents Grantslast 30 patents

Read threshold adjustment techniques for non-binary memory cells

Read threshold adjustment techniques for memory

Advanced bitwise operations and apparatus in a multi-level system w...

Read threshold adjustment techniques for non-binary memory cells

Memory cell state in a valley between adjacent data states

Read threshold adjustment techniques for memory

Efficient scrambling and encoding for copyback procedures using pre...

Advanced bitwise operations and apparatus in a multi-level system w...

Efficient scrambling and encoding for copyback procedures using pre...

Efficient scrambling and encoding for copyback procedures in a memo...

Memory cell state in a valley between adjacent data states

Advanced bitwise operations and apparatus in a multi-level system w...

Progressive effort decoder architecture

Bitwise operations and apparatus in a multi-level system

Determining whether a memory cell state is in a valley between adja...

Progressive effort decoder architecture

Advanced bitwise operations and apparatus in a multi-level system w...

Bitwise operations and apparatus in a multi-level system

Determining whether a memory cell state is in a valley between adja...

Advanced converters for memory cell sensing and methods

Bitwise operations and apparatus in a multi-level system

Advanced bitwise operations and apparatus in a multi-level system w...

Advanced converters for memory cell sensing and methods

Digital full-duplex transceiver

Patents Applicationslast 30 patents

READ THRESHOLD ADJUSTMENT TECHNIQUES FOR NON-BINARY MEMORY CELLS

READ THRESHOLD ADJUSTMENT TECHNIQUES FOR MEMORY

READ THRESHOLD ADJUSTMENT TECHNIQUES FOR NON-BINARY MEMORY CELLS

ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM W...

EFFICIENT SCRAMBLING AND ENCODING FOR COPYBACK PROCEDURES USING PRE...

MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES

MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES

PROGRESSIVE EFFORT DECODER ARCHITECTURE

ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM W...

BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM

PROGRESSIVE EFFORT DECODER ARCHITECTURE

DETERMINING WHETHER A MEMORY CELL STATE IS IN A VALLEY BETWEEN ADJA...

BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM

ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM W...

MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES

ADVANCED CONVERTERS FOR MEMORY CELL SENSING AND METHODS

ADVANCED CONVERTERS FOR MEMORY CELL SENSING AND METHODS

Advanced Bitwise Operations and Apparatus in a Multi-Level System w...

Bitwise Operations and Apparatus in a Multi-Level System