Robert B. Johnson

Person

Billerica, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Pause apparatus for a memory controller with interleaved queuing ap...
- Patent number 4,558,429
- Issue date Dec 10, 1985
- Honeywell Information Systems Inc.
- George J. Barlow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory identification apparatus and method
- Patent number 4,545,010
- Issue date Oct 1, 1985
- Honeywell Information Systems Inc.
- Edward R. Salas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system with automatic memory configuration
- Patent number 4,507,730
- Issue date Mar 26, 1985
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identification apparatus for use in a controller to facilitate the...
- Patent number 4,468,731
- Issue date Aug 28, 1984
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with interleaved queuing apparatus
- Patent number 4,451,880
- Issue date May 29, 1984
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential word aligned addressing apparatus
- Patent number 4,432,055
- Issue date Feb 14, 1984
- Honeywell Information Systems Inc.
- Edward R. Salas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for deferring error detection of multibyte parity encoded...
- Patent number 4,388,684
- Issue date Jun 14, 1983
- Honeywell Information Systems Inc.
- Chester M. Nibby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential word aligned address apparatus
- Patent number 4,376,972
- Issue date Mar 15, 1983
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with address independent burst mode capability
- Patent number 4,370,712
- Issue date Jan 25, 1983
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Soft error rewrite control system
- Patent number 4,369,510
- Issue date Jan 18, 1983
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with queue control apparatus
- Patent number 4,366,538
- Issue date Dec 28, 1982
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with burst mode capability
- Patent number 4,366,539
- Issue date Dec 28, 1982
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multimode memory system using a multiword common bus for double wor...
- Patent number 4,361,869
- Issue date Nov 30, 1982
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing and verifying the operation of err...
- Patent number 4,359,771
- Issue date Nov 16, 1982
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential chip select decode apparatus and method
- Patent number 4,323,965
- Issue date Apr 6, 1982
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double word fetch system
- Patent number 4,319,324
- Issue date Mar 9, 1982
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay line compensation network
- Patent number 4,302,735
- Issue date Nov 24, 1981
- Honeywell Information Systems Inc.
- Chester M. Nibby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of constructing a number of different memory systems
- Patent number 4,255,852
- Issue date Mar 17, 1981
- Honeywell Information Systems Inc.
- Robert B. Johnson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
System providing multiple fetch bus cycle operation
- Patent number 4,236,203
- Issue date Nov 25, 1980
- Honeywell Information Systems Inc.
- John L. Curley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Printed circuit board apparatus which facilitates fabrication of un...
- Patent number 4,190,901
- Issue date Feb 26, 1980
- Honeywell Information Systems Inc.
- Robert B. Johnson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Dynamic memory system which includes apparatus for performing refre...
- Patent number 4,185,323
- Issue date Jan 22, 1980
- Honeywell Information Systems Inc.
- Robert B. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for generating timing signals for latched type...
- Patent number 4,060,794
- Issue date Nov 29, 1977
- Honeywell Information Systems Inc.
- Paul S. Feldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power strobing to achieve a tri state
- Patent number 4,044,330
- Issue date Aug 23, 1977
- Honeywell Information Systems, Inc.
- Robert B. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Substrate bias voltage generated from refresh oscillator
- Patent number 4,030,084
- Issue date Jun 14, 1977
- Honeywell Information Systems, Inc.
- Edwin P. Fisher
- G05 - CONTROLLING REGULATING
Information Patent Grant
Apparatus for enhancing output characteristics of voltage driver ci...
- Patent number 3,967,139
- Issue date Jun 29, 1976
- Honeywell Information Systems, Inc.
- Robert B. Johnson
- G11 - INFORMATION STORAGE

Robert B. Johnson

Person

Patents Grantslast 30 patents

Pause apparatus for a memory controller with interleaved queuing ap...

Memory identification apparatus and method

Memory system with automatic memory configuration

Identification apparatus for use in a controller to facilitate the...

Memory controller with interleaved queuing apparatus

Sequential word aligned addressing apparatus

Apparatus for deferring error detection of multibyte parity encoded...

Sequential word aligned address apparatus

Memory controller with address independent burst mode capability

Soft error rewrite control system

Memory controller with queue control apparatus

Memory controller with burst mode capability

Multimode memory system using a multiword common bus for double wor...

Method and apparatus for testing and verifying the operation of err...

Sequential chip select decode apparatus and method

Double word fetch system

Delay line compensation network

Method of constructing a number of different memory systems

System providing multiple fetch bus cycle operation

Printed circuit board apparatus which facilitates fabrication of un...

Dynamic memory system which includes apparatus for performing refre...

Apparatus and method for generating timing signals for latched type...

Power strobing to achieve a tri state

Substrate bias voltage generated from refresh oscillator

Apparatus for enhancing output characteristics of voltage driver ci...