Robert Baltar

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wear leveling for a memory device
- Patent number 9,710,376
- Issue date Jul 18, 2017
- Micron Technology, Inc.
- Robert Baltar
- G11 - INFORMATION STORAGE
Information Patent Grant
Wear leveling for a memory device
- Patent number 9,104,547
- Issue date Aug 11, 2015
- Micron Technology, Inc.
- Robert Baltar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Kicker for non-volatile memory drain bias
- Patent number 6,744,671
- Issue date Jun 1, 2004
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential redundancy multiplexor for flash memory devices
- Patent number 6,574,141
- Issue date Jun 3, 2003
- Intel Corporation
- Robert L. Baltar
- G11 - INFORMATION STORAGE
Information Patent Grant
Load for non-volatile memory drain bias
- Patent number 6,570,789
- Issue date May 27, 2003
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
Drain bias for non-volatile memory
- Patent number 6,535,423
- Issue date Mar 18, 2003
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for gating a global column select line with ad...
- Patent number 6,456,540
- Issue date Sep 24, 2002
- Intel Corporation
- Robert Baltar
- G11 - INFORMATION STORAGE
Information Patent Grant
Computing system with volatile lock architecture for individual blo...
- Patent number 6,446,179
- Issue date Sep 3, 2002
- Intel Corporation
- Robert L. Baltar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential signal path for high speed data transmission in flash...
- Patent number 6,442,069
- Issue date Aug 27, 2002
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Sample and hold voltage reference source
- Patent number 6,434,049
- Issue date Aug 13, 2002
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
Preventing data corruption in a memory device using a modified memo...
- Patent number 6,212,099
- Issue date Apr 3, 2001
- Intel Corporation
- Suibin Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus using volatile lock architecture for individua...
- Patent number 6,209,069
- Issue date Mar 27, 2001
- Intel Corporation
- Robert L. Baltar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonvolatile memory blocking architecture
- Patent number 5,663,923
- Issue date Sep 2, 1997
- Intel Corporation
- Robert L. Baltar
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual row selection using multiplexed tri-level decoder
- Patent number 5,517,138
- Issue date May 14, 1996
- Intel Corporation
- Robert L. Baltar
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
WEAR LEVELING FOR A MEMORY DEVICE
- Publication number 20150301937
- Publication date Oct 22, 2015
- Micron Technology, Inc.
- Robert Baltar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WEAR LEVELING FOR A MEMORY DEVICE
- Publication number 20130036253
- Publication date Feb 7, 2013
- Micron Technology, Inc.
- Robert Baltar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Load for non-volatile memory drain bias
- Publication number 20020126527
- Publication date Sep 12, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR GATING A GLOBAL COLUMN SELECT LINE WITH AD...
- Publication number 20020101766
- Publication date Aug 1, 2002
- Robert Baltar
- G11 - INFORMATION STORAGE
Information Patent Application
Differential redundancy multiplexor for flash memory devices
- Publication number 20020085415
- Publication date Jul 4, 2002
- Robert L. Baltar
- G11 - INFORMATION STORAGE
Information Patent Application
SAMPLE AND HOLD VOLTAGE REFERENCE SOURCE
- Publication number 20020085413
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
Drain bias for non-volatile memory
- Publication number 20020085421
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
Drain bias for non-volatile memory
- Publication number 20020085422
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
DIFFERENTIAL SIGNAL PATH FOR HIGH SPEED DATA TRANSMISSION IN FLASH...
- Publication number 20020085425
- Publication date Jul 4, 2002
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
Volatile lock architecture for individual block locking on flash me...
- Publication number 20010000816
- Publication date May 3, 2001
- Robert L. Baltar
- G06 - COMPUTING CALCULATING COUNTING

Robert Baltar

Person

Patents Grantslast 30 patents

Wear leveling for a memory device

Wear leveling for a memory device

Kicker for non-volatile memory drain bias

Differential redundancy multiplexor for flash memory devices

Load for non-volatile memory drain bias

Drain bias for non-volatile memory

Method and apparatus for gating a global column select line with ad...

Computing system with volatile lock architecture for individual blo...

Differential signal path for high speed data transmission in flash...

Sample and hold voltage reference source

Preventing data corruption in a memory device using a modified memo...

Method and apparatus using volatile lock architecture for individua...

Nonvolatile memory blocking architecture

Dual row selection using multiplexed tri-level decoder

Patents Applicationslast 30 patents

WEAR LEVELING FOR A MEMORY DEVICE

WEAR LEVELING FOR A MEMORY DEVICE

Load for non-volatile memory drain bias

METHOD AND APPARATUS FOR GATING A GLOBAL COLUMN SELECT LINE WITH AD...

Differential redundancy multiplexor for flash memory devices

SAMPLE AND HOLD VOLTAGE REFERENCE SOURCE

Drain bias for non-volatile memory

Drain bias for non-volatile memory

DIFFERENTIAL SIGNAL PATH FOR HIGH SPEED DATA TRANSMISSION IN FLASH...

Volatile lock architecture for individual block locking on flash me...