Robert Brett Tremaine

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Functional built-in self test for a chip
- Patent number 9,384,108
- Issue date Jul 5, 2016
- International Business Machines Corporation
- Kevin M. McIlvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable differential to single ended IO
- Patent number 9,325,534
- Issue date Apr 26, 2016
- International Business Machines Corporation
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable logic circuit using three-dimensional stacking techniques
- Patent number 9,300,298
- Issue date Mar 29, 2016
- International Business Machines Corporation
- Edgar R. Cordero
- G11 - INFORMATION STORAGE
Information Patent Grant
Soft error resilient FPGA
- Patent number 9,166,587
- Issue date Oct 20, 2015
- International Business Machines Corporation
- Luiz C. Alves
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data compression utilizing longest common subsequence template
- Patent number 9,106,251
- Issue date Aug 11, 2015
- International Business Machines Corporation
- Kanak B. Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Selective recompression of a string compressed by a plurality of di...
- Patent number 9,106,252
- Issue date Aug 11, 2015
- International Business Machines Corporation
- Kanak B. Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Requesting a memory space by a memory controller
- Patent number 9,086,957
- Issue date Jul 21, 2015
- International Business Machines Corporation
- Edgar R. Cordero
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Accessing additional memory space with multiple processors
- Patent number 9,052,840
- Issue date Jun 9, 2015
- International Business Machines Corporation
- Edgar R. Cordero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accessing additional memory space with multiple processors
- Patent number 9,047,057
- Issue date Jun 2, 2015
- International Business Machines Corporation
- Edgar R. Cordero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assist thread for injecting cache memory in a microprocessor
- Patent number 8,949,837
- Issue date Feb 3, 2015
- International Business Machines Corporation
- Patrick Joseph Bohrer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quality of service scheduling for simultaneous multi-threaded proce...
- Patent number 8,869,153
- Issue date Oct 21, 2014
- International Business Machines Corporation
- Orran Y. Krieger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory package utilizing at least two types of memories
- Patent number 8,850,115
- Issue date Sep 30, 2014
- International Business Machines Corporation
- Robert B. Tremaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch engine based translation prefetching
- Patent number 8,806,177
- Issue date Aug 12, 2014
- International Business Machines Corporation
- Orran Y. Krieger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing chip to chip calibration within a TSV stack
- Patent number 8,692,561
- Issue date Apr 8, 2014
- International Business Machines Corporation
- Edgar R. Cordero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data compression utilizing longest common subsequence template
- Patent number 8,674,856
- Issue date Mar 18, 2014
- International Business Machines Corporation
- Kanak B. Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Selective recompression of a string compressed by a plurality of di...
- Patent number 8,618,960
- Issue date Dec 31, 2013
- International Business Machines Corporation
- Kanak B. Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory architecture with policy based data storage
- Patent number 8,595,463
- Issue date Nov 26, 2013
- International Business Machines Corporation
- Robert B. Tremaine
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Verification of soft error resilience
- Patent number 8,555,234
- Issue date Oct 8, 2013
- International Business Machines Corporation
- Robert Brett Tremaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing vertical die stacking to distribute logical function o...
- Patent number 8,516,409
- Issue date Aug 20, 2013
- International Business Machines Corporation
- Paul W. Coteus
- G11 - INFORMATION STORAGE
Information Patent Grant
Soft error resilient FPGA
- Patent number 8,513,972
- Issue date Aug 20, 2013
- International Business Machines Corporation
- Luiz C. Alves
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory page management in a tiered memory system
- Patent number 8,495,318
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Robert B. Tremaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing frame start indication in a memory system having indeterm...
- Patent number 8,495,328
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Strobe offset in bidirectional memory strobe configurations
- Patent number 8,493,801
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Daniel M. Dreps
- G11 - INFORMATION STORAGE
Information Patent Grant
Scheduling threads having complementary functional unit usage on SM...
- Patent number 8,495,649
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Orran Y. Krieger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic circuit using three-dimensional stacking techniques
- Patent number 8,493,089
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Edgar R. Cordero
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for software-assisted data cache and prefetch...
- Patent number 8,490,065
- Issue date Jul 16, 2013
- International Business Machines Corporation
- Roch Archambault
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System to determine fault tolerance in an integrated circuit and as...
- Patent number 8,433,950
- Issue date Apr 30, 2013
- International Business Machines Corporation
- Mark A. Check
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing frame start indication in a memory system having indeterm...
- Patent number 8,327,105
- Issue date Dec 4, 2012
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Strobe offset in bidirectional memory strobe configurations
- Patent number 8,284,621
- Issue date Oct 9, 2012
- International Business Machines Corporation
- Daniel M. Dreps
- G11 - INFORMATION STORAGE
Information Patent Grant
Assist thread for injecting cache memory in a microprocessor
- Patent number 8,230,422
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Patrick Joseph Bohrer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FUNCTIONAL BUILT-IN SELF TEST FOR A CHIP
- Publication number 20140156253
- Publication date Jun 5, 2014
- International Business Machines Corporation
- Kevin M. McIlvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESSING ADDITIONAL MEMORY SPACE WITH MULTIPLE PROCESSORS
- Publication number 20140143512
- Publication date May 22, 2014
- International Business Machines Corporation
- Edgar R. Cordero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESSING ADDITIONAL MEMORY SPACE WITH MULTIPLE PROCESSORS
- Publication number 20140143510
- Publication date May 22, 2014
- International Business Machines Corporation
- Edgar R. Cordero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE RECOMPRESSION OF A STRING COMPRESSED BY A PLURALITY OF DI...
- Publication number 20140049410
- Publication date Feb 20, 2014
- KANAK B. AGARWAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATA COMPRESSION UTILIZING LONGEST COMMON SUBSEQUENCE TEMPLATE
- Publication number 20140049412
- Publication date Feb 20, 2014
- International Business Machines Corporation
- Kanak B. Agarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATA COMPRESSION UTILIZING LONGEST COMMON SUBSEQUENCE TEMPLATE
- Publication number 20140049413
- Publication date Feb 20, 2014
- KANAK B. AGARWAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REQUESTING A MEMORY SPACE BY A MEMORY CONTROLLER
- Publication number 20140040576
- Publication date Feb 6, 2014
- International Business Machines Corporation
- Edgar R. Cordero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC CIRCUIT USING THREE-DIMENSIONAL STACKING TECHNIQUES
- Publication number 20130275823
- Publication date Oct 17, 2013
- Edgar R. Cordero
- G11 - INFORMATION STORAGE
Information Patent Application
SOFT ERROR RESILIENT FPGA
- Publication number 20130265080
- Publication date Oct 10, 2013
- Luiz C. Alves
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HOST-SIDE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS
- Publication number 20130262791
- Publication date Oct 3, 2013
- International Business Machines Corporation
- Joab D. Henderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY S...
- Publication number 20130262792
- Publication date Oct 3, 2013
- International Business Machines Corporation
- John E. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFT ERROR RESILIENT FPGA
- Publication number 20130181738
- Publication date Jul 18, 2013
- International Business Machines Corporation
- Luiz C. Alves
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK
- Publication number 20130038380
- Publication date Feb 14, 2013
- International Business Machines Corporation
- Edgar R. Cordero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Strobe Offset in Bidirectional Memory Strobe Configurations
- Publication number 20120300564
- Publication date Nov 29, 2012
- International Business Machines Corporation
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC CIRCUIT USING THREE-DIMENSIONAL STACKING TECHNIQUES
- Publication number 20120256653
- Publication date Oct 11, 2012
- International Business Machines Corporation
- Edgar R. Cordero
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory Package Utilizing At Least Two Types of Memories
- Publication number 20120198143
- Publication date Aug 2, 2012
- International Business Machines Corporation
- Robert B. Tremaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASSIST THREAD FOR INJECTING CACHE MEMORY IN A MICROPROCESSOR
- Publication number 20120198459
- Publication date Aug 2, 2012
- International Business Machines Corporation
- Patrick Joseph Bohrer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERM...
- Publication number 20120151171
- Publication date Jun 14, 2012
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERM...
- Publication number 20120151172
- Publication date Jun 14, 2012
- International Business Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING VERTICAL DIE STACKING TO DISTRIBUTE LOGICAL FUNCTION O...
- Publication number 20120124532
- Publication date May 17, 2012
- International Business Machines Corporation
- Paul W. Coteus
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Architecture with Policy Based Data Storage
- Publication number 20120066473
- Publication date Mar 15, 2012
- International Business Machines Corporation
- Robert B. Tremaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PAGE MANAGEMENT IN A TIERED MEMORY SYSTEM
- Publication number 20120023300
- Publication date Jan 26, 2012
- International Business Machines Corporation
- Robert B. Tremaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPPORTUNISTIC BUS ACCESS LATENCY
- Publication number 20110234259
- Publication date Sep 29, 2011
- International Business Machines Corporation
- Theodore P. Haggis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Strobe Offset in Bidirectional Memory Strobe Configurations
- Publication number 20110199843
- Publication date Aug 18, 2011
- International Business Machines Corporation
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combined Memory Including a Logical Partition in a Storage Memory A...
- Publication number 20110161597
- Publication date Jun 30, 2011
- International Business Machines Corporation
- Robert B. Tremaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling for functional units on simultaneous multi-threaded proc...
- Publication number 20110126200
- Publication date May 26, 2011
- International Business Machine Corporation
- Orran Y. Krieger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE RECONFIGURATION BASED ON RUN-TIME PERFORMANCE DATA OR SOFTWAR...
- Publication number 20110107032
- Publication date May 5, 2011
- International Business Machines Corporation
- Xiaowei Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Package Utilizing At Least Two Types of Memories
- Publication number 20110087834
- Publication date Apr 14, 2011
- International Business Machines Corporation
- Robert B. Tremaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable Differential to Single Ended IO
- Publication number 20110075740
- Publication date Mar 31, 2011
- International Business Machines Corporation
- Frank D. Ferraiolo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Verification of Soft Error Resilience
- Publication number 20110055777
- Publication date Mar 3, 2011
- International Business Machines Corporation
- Robert Brett Tremaine
- G06 - COMPUTING CALCULATING COUNTING

Robert Brett Tremaine

Person

Patents Grantslast 30 patents

Functional built-in self test for a chip

Configurable differential to single ended IO

Programmable logic circuit using three-dimensional stacking techniques

Soft error resilient FPGA

Data compression utilizing longest common subsequence template

Selective recompression of a string compressed by a plurality of di...

Requesting a memory space by a memory controller

Accessing additional memory space with multiple processors

Accessing additional memory space with multiple processors

Assist thread for injecting cache memory in a microprocessor

Quality of service scheduling for simultaneous multi-threaded proce...

Memory package utilizing at least two types of memories

Prefetch engine based translation prefetching

Implementing chip to chip calibration within a TSV stack

Data compression utilizing longest common subsequence template

Selective recompression of a string compressed by a plurality of di...

Memory architecture with policy based data storage

Verification of soft error resilience

Implementing vertical die stacking to distribute logical function o...

Soft error resilient FPGA

Memory page management in a tiered memory system

Providing frame start indication in a memory system having indeterm...

Strobe offset in bidirectional memory strobe configurations

Scheduling threads having complementary functional unit usage on SM...

Programmable logic circuit using three-dimensional stacking techniques

Method and apparatus for software-assisted data cache and prefetch...

System to determine fault tolerance in an integrated circuit and as...

Providing frame start indication in a memory system having indeterm...

Strobe offset in bidirectional memory strobe configurations

Assist thread for injecting cache memory in a microprocessor

Patents Applicationslast 30 patents

FUNCTIONAL BUILT-IN SELF TEST FOR A CHIP

ACCESSING ADDITIONAL MEMORY SPACE WITH MULTIPLE PROCESSORS

ACCESSING ADDITIONAL MEMORY SPACE WITH MULTIPLE PROCESSORS

SELECTIVE RECOMPRESSION OF A STRING COMPRESSED BY A PLURALITY OF DI...

DATA COMPRESSION UTILIZING LONGEST COMMON SUBSEQUENCE TEMPLATE

DATA COMPRESSION UTILIZING LONGEST COMMON SUBSEQUENCE TEMPLATE

REQUESTING A MEMORY SPACE BY A MEMORY CONTROLLER

PROGRAMMABLE LOGIC CIRCUIT USING THREE-DIMENSIONAL STACKING TECHNIQUES

SOFT ERROR RESILIENT FPGA

HOST-SIDE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS

MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY S...

SOFT ERROR RESILIENT FPGA

IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK

Strobe Offset in Bidirectional Memory Strobe Configurations

PROGRAMMABLE LOGIC CIRCUIT USING THREE-DIMENSIONAL STACKING TECHNIQUES

Memory Package Utilizing At Least Two Types of Memories

ASSIST THREAD FOR INJECTING CACHE MEMORY IN A MICROPROCESSOR

PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERM...

PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERM...

IMPLEMENTING VERTICAL DIE STACKING TO DISTRIBUTE LOGICAL FUNCTION O...

Memory Architecture with Policy Based Data Storage

MEMORY PAGE MANAGEMENT IN A TIERED MEMORY SYSTEM

OPPORTUNISTIC BUS ACCESS LATENCY

Strobe Offset in Bidirectional Memory Strobe Configurations

Combined Memory Including a Logical Partition in a Storage Memory A...

Scheduling for functional units on simultaneous multi-threaded proc...

CACHE RECONFIGURATION BASED ON RUN-TIME PERFORMANCE DATA OR SOFTWAR...

Memory Package Utilizing At Least Two Types of Memories

Configurable Differential to Single Ended IO

Verification of Soft Error Resilience