Robert Cassel

Person

Lehi, UT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Spike current suppression in a memory array
- Patent number 12,260,908
- Issue date Mar 25, 2025
- Micron Technology, Inc.
- Sundaravadivel Rajarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable resistivity for lines in a memory device
- Patent number 12,040,014
- Issue date Jul 16, 2024
- Micron Technology, Inc.
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge screening structure for spike current suppression in a memor...
- Patent number 11,984,161
- Issue date May 14, 2024
- Micron Technology, Inc.
- Srivatsan Venkatesan
- G11 - INFORMATION STORAGE
Information Patent Grant
Access line having a resistive layer for memory cell access
- Patent number 11,862,215
- Issue date Jan 2, 2024
- Micron Technology, Inc.
- Sateesh Talasila
- G11 - INFORMATION STORAGE
Information Patent Grant
Socket structure for spike current suppression in a memory array
- Patent number 11,715,520
- Issue date Aug 1, 2023
- Micron Technology, Inc.
- Robert Douglas Cassel
- G11 - INFORMATION STORAGE
Information Patent Grant
Spike current suppression in a memory array
- Patent number 11,514,985
- Issue date Nov 29, 2022
- Micron Technology, Inc.
- Sundaravadivel Rajarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable resistivity for lines in a memory device
- Patent number 11,495,293
- Issue date Nov 8, 2022
- Micron Technology, Inc.
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge screening structure for spike current suppression in a memor...
- Patent number 11,348,640
- Issue date May 31, 2022
- Micron Technology, Inc.
- Srivatsan Venkatesan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
FLASH MEMORY INCLUDING SELF-ALIGNED FLOATING GATES
- Publication number 20250176176
- Publication date May 29, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Robert Cassel
Information Patent Application
SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTO...
- Publication number 20250176201
- Publication date May 29, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Hiroshi Yasuda
Information Patent Application
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED NITRIDE FOR POWER ISOLATION
- Publication number 20250113558
- Publication date Apr 3, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Gowrisankar Damarla
Information Patent Application
CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE
- Publication number 20240379157
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE
- Publication number 20230114440
- Publication date Apr 13, 2023
- Micron Technology, Inc.
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Application
Access Line Having a Resistive Layer for Memory Cell Access
- Publication number 20230069190
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Sateesh Talasila
- G11 - INFORMATION STORAGE
Information Patent Application
SPIKE CURRENT SUPPRESSION IN A MEMORY ARRAY
- Publication number 20230018390
- Publication date Jan 19, 2023
- Micron Technology, Inc.
- Sundaravadivel Rajarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOCKET STRUCTURE FOR SPIKE CURRENT SUPPRESSION IN A MEMORY ARRAY
- Publication number 20220319595
- Publication date Oct 6, 2022
- Micron Technology, Inc.
- Robert Douglas Cassel
- G11 - INFORMATION STORAGE
Information Patent Application
SPIKE CURRENT SUPPRESSION IN A MEMORY ARRAY
- Publication number 20220319592
- Publication date Oct 6, 2022
- Micron Technology, Inc.
- Sundaravadivel Rajarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHARGE SCREENING STRUCTURE FOR SPIKE CURRENT SUPPRESSION IN A MEMOR...
- Publication number 20220319594
- Publication date Oct 6, 2022
- Micron Technology, Inc.
- Srivatsan Venkatesan
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE
- Publication number 20210241828
- Publication date Aug 5, 2021
- Micron Technology, Inc.
- Koushik Banerjee
- G11 - INFORMATION STORAGE

Robert Cassel

Person

Patents Grantslast 30 patents

Spike current suppression in a memory array

Configurable resistivity for lines in a memory device

Charge screening structure for spike current suppression in a memor...

Access line having a resistive layer for memory cell access

Socket structure for spike current suppression in a memory array

Spike current suppression in a memory array

Configurable resistivity for lines in a memory device

Charge screening structure for spike current suppression in a memor...

Patents Applicationslast 30 patents

FLASH MEMORY INCLUDING SELF-ALIGNED FLOATING GATES

SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTO...

SEMICONDUCTOR DEVICE WITH SELF-ALIGNED NITRIDE FOR POWER ISOLATION

CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE

CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE

Access Line Having a Resistive Layer for Memory Cell Access

SPIKE CURRENT SUPPRESSION IN A MEMORY ARRAY

SOCKET STRUCTURE FOR SPIKE CURRENT SUPPRESSION IN A MEMORY ARRAY

SPIKE CURRENT SUPPRESSION IN A MEMORY ARRAY

CHARGE SCREENING STRUCTURE FOR SPIKE CURRENT SUPPRESSION IN A MEMOR...

CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE