Robert D. Waldron

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data shredding RAID mode
- Patent number 8,806,227
- Issue date Aug 12, 2014
- LSI Corporation
- Mikhail I. Grinchuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of configurable mixed-signal building block functions to accomp...
- Patent number 7,478,354
- Issue date Jan 13, 2009
- LSI Corporation
- Donald T. McGrath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect integrity verification
- Patent number 7,424,690
- Issue date Sep 9, 2008
- LSI Corporation
- Richard T Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Relocatable built-in self test (BIST) elements for relocatable mixe...
- Patent number 7,373,622
- Issue date May 13, 2008
- LSI Logic Corporation
- Scott C. Savage
- G01 - MEASURING TESTING
Information Patent Grant
Distributed relocatable voltage regulator
- Patent number 7,373,629
- Issue date May 13, 2008
- LSI Logic Corporation
- Donald T. McGrath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mixed-signal functions using R-cells
- Patent number 7,360,178
- Issue date Apr 15, 2008
- LSI Logic Corporation
- Scott C. Savage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Relocatable mixed-signal functions
- Patent number 7,305,646
- Issue date Dec 4, 2007
- LSI Corporation
- Donald T. McGrath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of interconnect for multi-slot metal-mask programmable reloc...
- Patent number 7,292,063
- Issue date Nov 6, 2007
- LSI Corporation
- Scott C. Savage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concentric metal density power routing
- Patent number 6,476,497
- Issue date Nov 5, 2002
- LSI Logic Corporation
- Robert D. Waldron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single-edge triggered phase detector
- Patent number 5,754,080
- Issue date May 19, 1998
- AT&T Global Information Solutions Company
- Dao-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integral bit error rate test system for serial data communication l...
- Patent number 5,726,991
- Issue date Mar 10, 1998
- AT&T Global Information Solutions Company
- Dao-Long Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fast CMOS charge pump circuit
- Patent number 5,363,066
- Issue date Nov 8, 1994
- AT&T Global Information Solutions Company (fka NCR Corporation)
- Dao-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed current/voltage controlled ring oscillator circuit
- Patent number 5,300,898
- Issue date Apr 5, 1994
- NCR Corporation
- Dao-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device and method for approximating the square root of a number
- Patent number 5,268,857
- Issue date Dec 7, 1993
- NCR Corporation
- Dao-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage variable delay circuit
- Patent number 5,231,319
- Issue date Jul 27, 1993
- NCR Corporation
- Harold S. Crafts
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electrical connection between buses on a semiconductor integrated c...
- Patent number 5,185,652
- Issue date Feb 9, 1993
- NCR Corporation
- Robert D. Waldron
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High speed CMOS flip-flop employing clocked tristate inverters
- Patent number 5,140,180
- Issue date Aug 18, 1992
- NCR Corporation
- Harold S. Crafts
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Data Shredding RAID Mode
- Publication number 20080046764
- Publication date Feb 21, 2008
- LSI Logic Corporation
- Mikhail I. Grinchuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of interconnect for multi-slot metal-mask programmable reloc...
- Publication number 20060279326
- Publication date Dec 14, 2006
- LSI Logic Corporation
- Scott C. Savage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mixed-signal functions using R-cells
- Publication number 20060271901
- Publication date Nov 30, 2006
- LSI Logic Corporation
- Scott C. Savage
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Use of configurable mixed-signal building block functions to accomp...
- Publication number 20060263933
- Publication date Nov 23, 2006
- LSI Logic Corporation
- Donald T. McGrath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Relocatable built-in self test (BIST) elements for relocatable mixe...
- Publication number 20060259841
- Publication date Nov 16, 2006
- LSI Logic Corporation
- Scott C. Savage
- G01 - MEASURING TESTING
Information Patent Application
Relocatable mixed-signal functions
- Publication number 20060253825
- Publication date Nov 9, 2006
- LSI Logic Corporation
- Donald T. McGrath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distributed relocatable voltage regulator
- Publication number 20060239052
- Publication date Oct 26, 2006
- LSI Logic Corporation
- Donald T. McGrath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect integrity verification
- Publication number 20060123377
- Publication date Jun 8, 2006
- LSI Logic Corporation
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING

Robert D. Waldron

Person

Patents Grantslast 30 patents

Data shredding RAID mode

Use of configurable mixed-signal building block functions to accomp...

Interconnect integrity verification

Relocatable built-in self test (BIST) elements for relocatable mixe...

Distributed relocatable voltage regulator

Mixed-signal functions using R-cells

Relocatable mixed-signal functions

Method of interconnect for multi-slot metal-mask programmable reloc...

Concentric metal density power routing

Single-edge triggered phase detector

Integral bit error rate test system for serial data communication l...

Fast CMOS charge pump circuit

High speed current/voltage controlled ring oscillator circuit

Device and method for approximating the square root of a number

Voltage variable delay circuit

Electrical connection between buses on a semiconductor integrated c...

High speed CMOS flip-flop employing clocked tristate inverters

Patents Applicationslast 30 patents

Data Shredding RAID Mode

Method of interconnect for multi-slot metal-mask programmable reloc...

Mixed-signal functions using R-cells

Use of configurable mixed-signal building block functions to accomp...

Relocatable built-in self test (BIST) elements for relocatable mixe...

Relocatable mixed-signal functions

Distributed relocatable voltage regulator

Interconnect integrity verification