Robert Douglas CLANCY

Person

Cary, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processor branch prediction circuit employing back-invalidation of...
- Patent number 11,487,545
- Issue date Nov 1, 2022
- Microsoft Technology Licensing, LLC
- Daren E. Streett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operand-based reach explicit dataflow processors, and related metho...
- Patent number 10,956,162
- Issue date Mar 23, 2021
- Microsoft Technology Licensing, LLC
- Robert Douglas Clancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch prediction based on load-path history
- Patent number 10,838,731
- Issue date Nov 17, 2020
- QUALCOMM Incorporated
- Rami Mohammad A. Al Sheikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Precise invalidation of virtually tagged caches
- Patent number 10,318,436
- Issue date Jun 11, 2019
- QUALCOMM Incorporated
- William McAvoy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preventing the displacement of high temporal locality of reference...
- Patent number 10,114,750
- Issue date Oct 30, 2018
- QUALCOMM Incorporated
- Robert D. Clancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining cache hit/miss of aliased addresses in virtually-tagged...
- Patent number 9,110,830
- Issue date Aug 18, 2015
- QUALCOMM Incorporated
- James Norris Dieffenderfer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for filtering traffic to a physically-tagged data cache
- Patent number 8,612,690
- Issue date Dec 17, 2013
- QUALCOMM Incorporated
- Robert D. Clancy
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Latency insensitive FIFO signaling protocol
- Patent number 7,725,625
- Issue date May 25, 2010
- QUALCOMM Incorporated
- Kenneth Alan Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing cache partitioning using a dynami...
- Patent number 7,650,466
- Issue date Jan 19, 2010
- QUALCOMM Incorporated
- Brian Michael Stempel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency insensitive FIFO signaling protocol
- Patent number 7,454,538
- Issue date Nov 18, 2008
- QUALCOMM Incorporated
- Kenneth Alan Dockser
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROCESSOR SUPPORTING TRANSLATION LOOKASIDE BUFFER (TLB) MODIFICATIO...
- Publication number 20220318139
- Publication date Oct 6, 2022
- Microsoft Technology Licensing, LLC
- Thomas Philip SPEIER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOP BUFFERING EMPLOYING LOOP CHARACTERISTIC PREDICTION IN A PROCES...
- Publication number 20220283811
- Publication date Sep 8, 2022
- Microsoft Technology Licensing, LLC
- Rami Mohammad AL SHEIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR BRANCH PREDICTION CIRCUIT EMPLOYING BACK-INVALIDATION OF...
- Publication number 20220283819
- Publication date Sep 8, 2022
- Microsoft Technology Licensing, LLC
- Daren E. STREETT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPERAND-BASED REACH EXPLICIT DATAFLOW PROCESSORS, AND RELATED METHO...
- Publication number 20200409712
- Publication date Dec 31, 2020
- Microsoft Technology Licensing, LLC
- Robert Douglas CLANCY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH PREDICTION BASED ON LOAD-PATH HISTORY
- Publication number 20200089504
- Publication date Mar 19, 2020
- QUALCOMM Incorporated
- Rami Mohammad A. AL SHEIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING EARLY PIPELINE OPTIMIZATION OF CONDITIONAL INSTRUCTIONS I...
- Publication number 20190294443
- Publication date Sep 26, 2019
- QUALCOMM Incorporated
- Sandeep Suresh Navada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST PIPELINE RESTART IN PROCESSOR WITH DECOUPLED FETCHER
- Publication number 20190155608
- Publication date May 23, 2019
- QUALCOMM Incorporated
- Arthur PERAIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRECISE INVALIDATION OF VIRTUALLY TAGGED CACHES
- Publication number 20190034349
- Publication date Jan 31, 2019
- QUALCOMM Incorporated
- William MCAVOY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRECISE INVALIDATION OF VIRTUALLY TAGGED CACHES
- Publication number 20180089094
- Publication date Mar 29, 2018
- QUALCOMM Incorporated
- Robert Douglas CLANCY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH TARGET INSTRUCTION CACHE (BTIC) TO STORE A CONDITIONAL BRANC...
- Publication number 20170083333
- Publication date Mar 23, 2017
- QUALCOMM Incorporated
- Niket Kumar CHOUDHARY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Way Mispredict Mitigation on a Way Predicted Cache
- Publication number 20170046266
- Publication date Feb 16, 2017
- QUALCOMM Incorporated
- Michael Scott McIlvaine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR UPDATING REPLACEMENT POLICY INFORMATION FO...
- Publication number 20170046278
- Publication date Feb 16, 2017
- QUALCOMM Incorporated
- Robert Douglas CLANCY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATING WRONG-PATH EFFECTS IN BRANCH PREDICTION
- Publication number 20160350116
- Publication date Dec 1, 2016
- QUALCOMM Incorporated
- Vimal Kodandarama REDDY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH PREDICTION USING LEAST-RECENTLY-USED (LRU)-CLASS LINKED LIST...
- Publication number 20160055003
- Publication date Feb 25, 2016
- QUALCOMM Incorporated
- Robert Douglas Clancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREVENTING THE DISPLACEMENT OF HIGH TEMPORAL LOCALITY OF REFERENCE...
- Publication number 20130191559
- Publication date Jul 25, 2013
- QUALCOMM Incorporated
- Robert D. Clancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Filtering Traffic to a Physically-Tagged Data Cache
- Publication number 20130185473
- Publication date Jul 18, 2013
- QUALCOMM Incorporated
- Robert D. Clancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Determining Cache Hit/Miss of Aliased Addresses in Virtually-Tagged...
- Publication number 20130185520
- Publication date Jul 18, 2013
- QUALCOMM Incorporated
- James Norris Dieffenderfer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency Insensitive FIFO Signaling Protocol
- Publication number 20080281996
- Publication date Nov 13, 2008
- QUALCOMM Incorporated
- Kenneth Alan Dockser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for managing cache partitioning
- Publication number 20070067574
- Publication date Mar 22, 2007
- Brian Michael Stempel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency insensitive FIFO signaling protocol
- Publication number 20060259669
- Publication date Nov 16, 2006
- Kenneth Alan Dockser
- G06 - COMPUTING CALCULATING COUNTING

Robert Douglas CLANCY

Person

Patents Grantslast 30 patents

Processor branch prediction circuit employing back-invalidation of...

Operand-based reach explicit dataflow processors, and related metho...

Branch prediction based on load-path history

Precise invalidation of virtually tagged caches

Preventing the displacement of high temporal locality of reference...

Determining cache hit/miss of aliased addresses in virtually-tagged...

Method for filtering traffic to a physically-tagged data cache

Latency insensitive FIFO signaling protocol

Method and apparatus for managing cache partitioning using a dynami...

Latency insensitive FIFO signaling protocol

Patents Applicationslast 30 patents

PROCESSOR SUPPORTING TRANSLATION LOOKASIDE BUFFER (TLB) MODIFICATIO...

LOOP BUFFERING EMPLOYING LOOP CHARACTERISTIC PREDICTION IN A PROCES...

PROCESSOR BRANCH PREDICTION CIRCUIT EMPLOYING BACK-INVALIDATION OF...

OPERAND-BASED REACH EXPLICIT DATAFLOW PROCESSORS, AND RELATED METHO...

BRANCH PREDICTION BASED ON LOAD-PATH HISTORY

PROVIDING EARLY PIPELINE OPTIMIZATION OF CONDITIONAL INSTRUCTIONS I...

FAST PIPELINE RESTART IN PROCESSOR WITH DECOUPLED FETCHER

PRECISE INVALIDATION OF VIRTUALLY TAGGED CACHES

PRECISE INVALIDATION OF VIRTUALLY TAGGED CACHES

BRANCH TARGET INSTRUCTION CACHE (BTIC) TO STORE A CONDITIONAL BRANC...

Way Mispredict Mitigation on a Way Predicted Cache

METHOD AND APPARATUS FOR UPDATING REPLACEMENT POLICY INFORMATION FO...

MITIGATING WRONG-PATH EFFECTS IN BRANCH PREDICTION

BRANCH PREDICTION USING LEAST-RECENTLY-USED (LRU)-CLASS LINKED LIST...

PREVENTING THE DISPLACEMENT OF HIGH TEMPORAL LOCALITY OF REFERENCE...

Method for Filtering Traffic to a Physically-Tagged Data Cache

Determining Cache Hit/Miss of Aliased Addresses in Virtually-Tagged...

Latency Insensitive FIFO Signaling Protocol

Method and apparatus for managing cache partitioning

Latency insensitive FIFO signaling protocol