Robert E. Boone

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for analyzing placement context sensitivity of standard cells
- Patent number 8,661,393
- Issue date Feb 25, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Robert E. Boone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for designing an integrated circuit using inve...
- Patent number 8,370,773
- Issue date Feb 5, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Kevin Dean Lucas
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method and apparatus for designing and integrated circuit
- Patent number 8,175,737
- Issue date May 8, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Kevin Dean Lucas
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR ANALYZING PLACEMENT CONTEXT SENSITIVITY OF STANDARD CELLS
- Publication number 20140007029
- Publication date Jan 2, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Robert E. Boone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT
- Publication number 20100333048
- Publication date Dec 30, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Kevin Dean Lucas
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT
- Publication number 20100122224
- Publication date May 13, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Kevin Lucas
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD AND APPARATUS FOR DESIGNING AND INTEGRATED CIRCUIT
- Publication number 20090240364
- Publication date Sep 24, 2009
- Kevin Dean Lucas
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method of Making an Integrated Circuit
- Publication number 20080250374
- Publication date Oct 9, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Kevin D. Lucas
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method of designing a reticle and forming a semiconductor device th...
- Publication number 20040248016
- Publication date Dec 9, 2004
- Kevin D. Lucas
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Robert E. Boone

Person

Patents Grantslast 30 patents

Method for analyzing placement context sensitivity of standard cells

Method and apparatus for designing an integrated circuit using inve...

Method and apparatus for designing and integrated circuit

Patents Applicationslast 30 patents

METHOD FOR ANALYZING PLACEMENT CONTEXT SENSITIVITY OF STANDARD CELLS

METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT

METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT

METHOD AND APPARATUS FOR DESIGNING AND INTEGRATED CIRCUIT

Method of Making an Integrated Circuit

Method of designing a reticle and forming a semiconductor device th...