Robert Erickson

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Partitioning using a correlation meta-heuristic
- Patent number 10,318,690
- Issue date Jun 11, 2019
- Synopsys, Inc.
- Robert J. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clustering using N-dimensional placement
- Patent number 9,208,278
- Issue date Dec 8, 2015
- Synopsys, Inc.
- Robert J. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet switch based logic replication
- Patent number 9,052,357
- Issue date Jun 9, 2015
- Synopsys, Inc.
- Robert Erickson
- G01 - MEASURING TESTING
Information Patent Grant
Packet switch based logic replication
- Patent number 8,638,792
- Issue date Jan 28, 2014
- Synopsys, Inc.
- Robert Erickson
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for packet switch based logic replication
- Patent number 8,397,195
- Issue date Mar 12, 2013
- Synopsys, Inc.
- Robert Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for designing integrated circuits
- Patent number 7,631,282
- Issue date Dec 8, 2009
- Synopsys, Inc.
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for designing integrated circuits (ICs) wit...
- Patent number 7,454,732
- Issue date Nov 18, 2008
- Synopsys, Inc.
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for designing integrated circuits
- Patent number 7,275,233
- Issue date Sep 25, 2007
- Synplicity, Inc.
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for designing integrated circuits
- Patent number 7,010,769
- Issue date Mar 7, 2006
- Synplicity, Inc.
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for designing integrated circuits
- Patent number 6,978,430
- Issue date Dec 20, 2005
- Synplicity, Inc.
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for designing integrated circuits
- Patent number 6,668,364
- Issue date Dec 23, 2003
- Synplicity, Inc.
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for designing integrated circuits
- Patent number 6,519,754
- Issue date Feb 11, 2003
- Synplicity, Inc.
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for designing integrated circuits
- Patent number 6,438,735
- Issue date Aug 20, 2002
- Synplicity, Inc.
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Partitioning Using a Correlation Meta-Heuristic
- Publication number 20180068044
- Publication date Mar 8, 2018
- Synopsys, Inc.
- Robert J. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLUSTERING USING N-DIMENSIONAL PLACEMENT
- Publication number 20150007120
- Publication date Jan 1, 2015
- Synopsys, Inc.
- Robert J. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Packet Switch Based Logic Replication
- Publication number 20140137056
- Publication date May 15, 2014
- Synopsys, Inc.
- Robert Erickson
- G01 - MEASURING TESTING
Information Patent Application
Method and System for Packet Switch Based Logic Replication
- Publication number 20110184717
- Publication date Jul 28, 2011
- Robert Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Packet Switch Based Logic Replication
- Publication number 20110185241
- Publication date Jul 28, 2011
- Robert Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUITS
- Publication number 20070288871
- Publication date Dec 13, 2007
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for designing integrated circuits
- Publication number 20060053401
- Publication date Mar 9, 2006
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for designing integrated circuits
- Publication number 20040117756
- Publication date Jun 17, 2004
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for designing integrated circuits
- Publication number 20030149954
- Publication date Aug 7, 2003
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for designing integrated circuits
- Publication number 20030079195
- Publication date Apr 24, 2003
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for designing integrated circuits
- Publication number 20020194572
- Publication date Dec 19, 2002
- Synplicity, Inc.
- Kenneth S. McElvain
- G06 - COMPUTING CALCULATING COUNTING

Robert Erickson

Person

Patents Grantslast 30 patents

Partitioning using a correlation meta-heuristic

Clustering using N-dimensional placement

Packet switch based logic replication

Packet switch based logic replication

Method and system for packet switch based logic replication

Methods and apparatuses for designing integrated circuits

Methods and apparatuses for designing integrated circuits (ICs) wit...

Methods and apparatuses for designing integrated circuits

Methods and apparatuses for designing integrated circuits

Methods and apparatuses for designing integrated circuits

Methods and apparatuses for designing integrated circuits

Methods and apparatuses for designing integrated circuits

Methods and apparatuses for designing integrated circuits

Patents Applicationslast 30 patents

Partitioning Using a Correlation Meta-Heuristic

CLUSTERING USING N-DIMENSIONAL PLACEMENT

Packet Switch Based Logic Replication

Method and System for Packet Switch Based Logic Replication

Method and System for Packet Switch Based Logic Replication

METHODS AND APPARATUSES FOR DESIGNING INTEGRATED CIRCUITS

Methods and apparatuses for designing integrated circuits

Methods and apparatuses for designing integrated circuits

Methods and apparatuses for designing integrated circuits

Methods and apparatuses for designing integrated circuits

Methods and apparatuses for designing integrated circuits