Robert F. Damiano

Person

Hopewell Junction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for modeling an HDL design using symbolic simulation
- Patent number 8,306,802
- Issue date Nov 6, 2012
- Synopsys, Inc.
- Yunshan Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating a boolean SAT solver into a router
- Patent number 7,904,867
- Issue date Mar 8, 2011
- Synopsys, Inc.
- Jerry R. Burch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch modeling technique for formal verification
- Patent number 7,254,793
- Issue date Aug 7, 2007
- Synopsys, Inc.
- Yirng-An Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation-based functional verification of microcircuit designs
- Patent number 7,130,783
- Issue date Oct 31, 2006
- Synopsys, Inc.
- Kevin M. Harer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for solving constraints
- Patent number 7,107,553
- Issue date Sep 12, 2006
- Synopsys, Inc.
- Brian Eugene Lockyear
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive cell separation and circuit changes driven by maximum capa...
- Patent number 6,397,169
- Issue date May 28, 2002
- Synopsys, Inc.
- Narendra V. Shenoy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic synthesis for logic array modules
- Patent number 5,754,824
- Issue date May 19, 1998
- International Business Machines Corporation
- Robert Damiano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for mapping in logic synthesis by logic classification
- Patent number 5,537,330
- Issue date Jul 16, 1996
- International Business Machines Corporation
- Robert F. Damiano
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Integrating a boolean SAT solver into a router
- Publication number 20080250376
- Publication date Oct 9, 2008
- Jerry R. Burch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Modeling an HDL Design Using Symbolic Simulation
- Publication number 20080126066
- Publication date May 29, 2008
- Synopsys, Inc.
- Yunshan Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latch modeling technique for formal verification
- Publication number 20060190870
- Publication date Aug 24, 2006
- Synopsys, Inc.
- Yirng-An Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for solving constraints
- Publication number 20050044512
- Publication date Feb 24, 2005
- Brian Eugene Lockyear
- G06 - COMPUTING CALCULATING COUNTING

Robert F. Damiano

Person

Patents Grantslast 30 patents

Method for modeling an HDL design using symbolic simulation

Integrating a boolean SAT solver into a router

Latch modeling technique for formal verification

Simulation-based functional verification of microcircuit designs

Method and apparatus for solving constraints

Adaptive cell separation and circuit changes driven by maximum capa...

Logic synthesis for logic array modules

Method for mapping in logic synthesis by logic classification

Patents Applicationslast 30 patents

Integrating a boolean SAT solver into a router

Method for Modeling an HDL Design Using Symbolic Simulation

Latch modeling technique for formal verification

Method and apparatus for solving constraints