Robert Faber

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Refresh logic to refresh only memory cells having a first value
- Patent number 10,438,658
- Issue date Oct 8, 2019
- Intel Corporation
- Ningde Xie
- G11 - INFORMATION STORAGE
Information Patent Grant
Interface for storage device access over memory bus
- Patent number 10,025,737
- Issue date Jul 17, 2018
- Intel Corporation
- Shekoufeh Qawami
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Wear leveling based on a swapping operation between sets of physica...
- Patent number 9,971,685
- Issue date May 15, 2018
- Intel Corporation
- Jason A. Gayman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for entry to a lower power state for a memory device
- Patent number 9,916,104
- Issue date Mar 13, 2018
- Intel Corporation
- Sowmiya Jayachandran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for entry to a lower power state for a memory device
- Patent number 9,818,458
- Issue date Nov 14, 2017
- Intel Corporation
- Sowmiya Jayachandran
- G11 - INFORMATION STORAGE
Information Patent Grant
Generation of far memory access signals based on usage statistic tr...
- Patent number 9,600,407
- Issue date Mar 21, 2017
- Intel Corporation
- Robert Faber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible wear management for non-volatile memory
- Patent number 9,501,405
- Issue date Nov 22, 2016
- Intel Corporation
- Prashant S. Damle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refresh of data stored in a cross-point non-volatile memory
- Patent number 9,257,175
- Issue date Feb 9, 2016
- Intel Corporation
- Kiran Pangal
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient PCMS refresh mechanism
- Patent number 9,202,548
- Issue date Dec 1, 2015
- Intel Corporation
- Robert W. Faber
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory wear management
- Patent number 9,141,536
- Issue date Sep 22, 2015
- Intel Corporation
- Robert W. Faber
- G11 - INFORMATION STORAGE
Information Patent Grant
Interface for storage device access over memory bus
- Patent number 9,064,560
- Issue date Jun 23, 2015
- Intel Corporation
- Shekoufeh Qawami
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible wear management for non-volatile memory
- Patent number 9,032,137
- Issue date May 12, 2015
- Intel Corporation
- Prashant S. Damle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retry based protocol with source/receiver FIFO recovery and anti-st...
- Patent number 8,943,379
- Issue date Jan 27, 2015
- Intel Corporation
- James R. Vash
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for managing a NAND flash memory by paging segmen...
- Patent number 8,612,666
- Issue date Dec 17, 2013
- Intel Corporation
- Robert J. Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface for storage device access over memory bus
- Patent number 8,607,089
- Issue date Dec 10, 2013
- Intel Corporation
- Shekoufeh Qawami
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjustable programming speed for NAND memory devices
- Patent number 8,595,597
- Issue date Nov 26, 2013
- Intel Corporation
- Ningde Xie
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, apparatus and system for determining an identifier of a vol...
- Patent number 8,463,948
- Issue date Jun 11, 2013
- Intel Corporation
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NAND power fail recovery
- Patent number 8,316,257
- Issue date Nov 20, 2012
- Intel Corporation
- Robert Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NAND power fail recovery
- Patent number 7,941,692
- Issue date May 10, 2011
- Intel Corporation
- Robert Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to write to a non-volatile memory
- Patent number 7,797,479
- Issue date Sep 14, 2010
- Intel Corporation
- Sanjeev N. Trika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing the effect of write disturbs in polymer memories
- Patent number 7,719,878
- Issue date May 18, 2010
- Intel Corporation
- Richard L. Coulson
- G11 - INFORMATION STORAGE
Information Patent Grant
Maintaining write ordering in a system
- Patent number 7,640,395
- Issue date Dec 29, 2009
- Intel Corporation
- Richard L. Coulson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed and packed metadata structure for disk cache
- Patent number 7,533,215
- Issue date May 12, 2009
- Intel Corporation
- Robert W. Faber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recovering from a non-volatile memory failure
- Patent number 7,516,267
- Issue date Apr 7, 2009
- Intel Corporation
- Richard L. Coulson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating pseudo random numbers in a vide...
- Patent number 7,426,274
- Issue date Sep 16, 2008
- Intel Corporation
- Robert W. Faber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface for a block addressable mass storage system
- Patent number 7,328,304
- Issue date Feb 5, 2008
- Intel Corporation
- Robert J. Royer, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing the effect of write disturbs in polymer memories
- Patent number 7,286,387
- Issue date Oct 23, 2007
- Intel Corporation
- Richard L. Coulson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for preservation of failure state in a read de...
- Patent number 7,168,026
- Issue date Jan 23, 2007
- Intel Corporation
- John I. Garney
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for determining scope of content domain
- Patent number 7,114,168
- Issue date Sep 26, 2006
- Intel Corporation
- David A. Wyatt
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dual use block/stream cipher
- Patent number 7,068,786
- Issue date Jun 27, 2006
- Intel Corporation
- Gary L. Graunke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
WEAR LEVELING BASED ON A SWAPPING OPERATION BETWEEN SETS OF PHYSICA...
- Publication number 20170286293
- Publication date Oct 5, 2017
- Intel Corporation
- Jason A. Gayman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR ENTRY TO A LOWER POWER STATE FOR A MEMORY DEVICE
- Publication number 20170115916
- Publication date Apr 27, 2017
- Intel Corporation
- Sowmiya Jayachandran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH LOGIC TO REFRESH ONLY MEMORY CELLS HAVING A FIRST VALUE
- Publication number 20160189774
- Publication date Jun 30, 2016
- Intel Corporation
- Ningde XIE
- G11 - INFORMATION STORAGE
Information Patent Application
FLEXIBLE WEAR MANAGEMENT FOR NON-VOLATILE MEMORY
- Publication number 20150309926
- Publication date Oct 29, 2015
- Intel Corporation
- Prashant S. Damle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS
- Publication number 20150269100
- Publication date Sep 24, 2015
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH OF DATA STORED IN A CROSS-POINT NON-VOLATILE MEMORY
- Publication number 20150089120
- Publication date Mar 26, 2015
- Intel Corporation
- Kiran Pangal
- G11 - INFORMATION STORAGE
Information Patent Application
METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH...
- Publication number 20140317337
- Publication date Oct 23, 2014
- Leena K. Puthiyedath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT PCMS REFRESH MECHANISM
- Publication number 20140204663
- Publication date Jul 24, 2014
- Robert W. Faber
- G11 - INFORMATION STORAGE
Information Patent Application
FLEXIBLE WEAR MANAGEMENT FOR NON-VOLATILE MEMORY
- Publication number 20140143474
- Publication date May 22, 2014
- Prashant S. Damle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS
- Publication number 20140075107
- Publication date Mar 13, 2014
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATION OF FAR MEMORY ACCESS SIGNALS BASED ON USAGE STATISTIC TR...
- Publication number 20130290597
- Publication date Oct 31, 2013
- Intel Corporation
- Robert Faber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NONVOLATILE MEMORY WEAR MANAGEMENT
- Publication number 20130268725
- Publication date Oct 10, 2013
- Robert W. Faber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interface for Storage Device Access Over Memory Bus
- Publication number 20120297231
- Publication date Nov 22, 2012
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTABLE PROGRAMMING SPEED FOR NAND MEMORY DEVICES
- Publication number 20120226959
- Publication date Sep 6, 2012
- Ningde Xie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NAND POWER FAIL RECOVERY
- Publication number 20110258487
- Publication date Oct 20, 2011
- Robert Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETRY BASED PROTOCOL WITH SOURCE/RECEIVER FIFO RECOVERY AND ANTI-ST...
- Publication number 20110161769
- Publication date Jun 30, 2011
- James R. Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR MANAGING A NAND FLASH MEMORY
- Publication number 20100332730
- Publication date Dec 30, 2010
- Robert J. Royer, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NAND error management
- Publication number 20090327837
- Publication date Dec 31, 2009
- Robert Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NAND power fail recovery
- Publication number 20090172466
- Publication date Jul 2, 2009
- Robert Royer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMAND COMPLETION DETECTION IN A MASS STORAGE DEVICE
- Publication number 20090172213
- Publication date Jul 2, 2009
- Sowmiya Jayachandran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing the effect of write disturbs in polymer memories
- Publication number 20070297212
- Publication date Dec 27, 2007
- Richard L. Coulson
- G11 - INFORMATION STORAGE
Information Patent Application
Maintaining write ordering in a system
- Publication number 20070233947
- Publication date Oct 4, 2007
- Richard L. Coulson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Recovering from a non-volatile memory failure
- Publication number 20070168698
- Publication date Jul 19, 2007
- Richard L. Coulson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method to enable fast disk caching and efficient operations on soli...
- Publication number 20070094445
- Publication date Apr 26, 2007
- Sanjeev N. Trika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distributed and packed metadata structure for disk cache
- Publication number 20070061511
- Publication date Mar 15, 2007
- Robert W. Faber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique to write to a non-volatile memory
- Publication number 20070005928
- Publication date Jan 4, 2007
- Sanjeev N. Trika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Speculative writeback for read destructive memory
- Publication number 20060277367
- Publication date Dec 7, 2006
- Robert W. Faber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Blank memory location detection mechanism
- Publication number 20060277359
- Publication date Dec 7, 2006
- Robert W. Faber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing the effect of write disturbs in polymer memories
- Publication number 20050207206
- Publication date Sep 22, 2005
- Richard L. Coulson
- G11 - INFORMATION STORAGE
Information Patent Application
Interface for a block addressable mass storage system
- Publication number 20050193164
- Publication date Sep 1, 2005
- Robert J. Royer
- G06 - COMPUTING CALCULATING COUNTING

Robert Faber

Person

Patents Grantslast 30 patents

Refresh logic to refresh only memory cells having a first value

Interface for storage device access over memory bus

Wear leveling based on a swapping operation between sets of physica...

Techniques for entry to a lower power state for a memory device

Techniques for entry to a lower power state for a memory device

Generation of far memory access signals based on usage statistic tr...

Flexible wear management for non-volatile memory

Refresh of data stored in a cross-point non-volatile memory

Efficient PCMS refresh mechanism

Nonvolatile memory wear management

Interface for storage device access over memory bus

Flexible wear management for non-volatile memory

Retry based protocol with source/receiver FIFO recovery and anti-st...

Method and system for managing a NAND flash memory by paging segmen...

Interface for storage device access over memory bus

Adjustable programming speed for NAND memory devices

Method, apparatus and system for determining an identifier of a vol...

NAND power fail recovery

NAND power fail recovery

Technique to write to a non-volatile memory

Reducing the effect of write disturbs in polymer memories

Maintaining write ordering in a system

Distributed and packed metadata structure for disk cache

Recovering from a non-volatile memory failure

Method and apparatus for generating pseudo random numbers in a vide...

Interface for a block addressable mass storage system

Reducing the effect of write disturbs in polymer memories

Method and apparatus for preservation of failure state in a read de...

Method and apparatus for determining scope of content domain

Dual use block/stream cipher

Patents Applicationslast 30 patents

WEAR LEVELING BASED ON A SWAPPING OPERATION BETWEEN SETS OF PHYSICA...

TECHNIQUES FOR ENTRY TO A LOWER POWER STATE FOR A MEMORY DEVICE

REFRESH LOGIC TO REFRESH ONLY MEMORY CELLS HAVING A FIRST VALUE

FLEXIBLE WEAR MANAGEMENT FOR NON-VOLATILE MEMORY

INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS

REFRESH OF DATA STORED IN A CROSS-POINT NON-VOLATILE MEMORY

METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH...

EFFICIENT PCMS REFRESH MECHANISM

FLEXIBLE WEAR MANAGEMENT FOR NON-VOLATILE MEMORY

INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS

GENERATION OF FAR MEMORY ACCESS SIGNALS BASED ON USAGE STATISTIC TR...

NONVOLATILE MEMORY WEAR MANAGEMENT

Interface for Storage Device Access Over Memory Bus

ADJUSTABLE PROGRAMMING SPEED FOR NAND MEMORY DEVICES

NAND POWER FAIL RECOVERY

RETRY BASED PROTOCOL WITH SOURCE/RECEIVER FIFO RECOVERY AND ANTI-ST...

METHOD AND SYSTEM FOR MANAGING A NAND FLASH MEMORY

NAND error management

NAND power fail recovery

COMMAND COMPLETION DETECTION IN A MASS STORAGE DEVICE

Reducing the effect of write disturbs in polymer memories

Maintaining write ordering in a system

Recovering from a non-volatile memory failure

Method to enable fast disk caching and efficient operations on soli...

Distributed and packed metadata structure for disk cache

Technique to write to a non-volatile memory

Speculative writeback for read destructive memory

Blank memory location detection mechanism

Reducing the effect of write disturbs in polymer memories

Interface for a block addressable mass storage system