Robert Farrell

Person

Granite Bay, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Technique to share information among different cache coherency domains
- Patent number 10,204,051
- Issue date Feb 12, 2019
- Intel Corporation
- Zeev Offen
- G11 - INFORMATION STORAGE
Information Patent Grant
Technique to share information among different cache coherency domains
- Patent number 10,078,590
- Issue date Sep 18, 2018
- Intel Corporation
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized depth buffer cache apparatus and method
- Patent number 10,002,455
- Issue date Jun 19, 2018
- Intel Corporation
- Robert L. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to share information among different cache coherency domains
- Patent number 9,946,650
- Issue date Apr 17, 2018
- Intel Corporation
- Zeev Offen
- G11 - INFORMATION STORAGE
Information Patent Grant
Position-only shading pipeline
- Patent number 9,824,412
- Issue date Nov 21, 2017
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to share information among different cache coherency domains
- Patent number 9,665,488
- Issue date May 30, 2017
- Intel Corporation
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Four corner high performance depth test
- Patent number 9,569,882
- Issue date Feb 14, 2017
- Intel Corporation
- Robert L. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constant buffer size multi-sampled anti-aliasing depth compression
- Patent number 9,412,195
- Issue date Aug 9, 2016
- Intel Corporation
- Robert L. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to share information among different cache coherency domains
- Patent number 9,035,959
- Issue date May 19, 2015
- Intel Corporation
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to share information among different cache coherency domains
- Patent number 9,035,962
- Issue date May 19, 2015
- Intel Corporation
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to share information among different cache coherency domains
- Patent number 9,035,960
- Issue date May 19, 2015
- Intel Corporation
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for safe enqueuing of events
- Patent number 8,813,083
- Issue date Aug 19, 2014
- Intel Corporation
- Robert L. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to share information among different cache coherency domains
- Patent number 8,643,660
- Issue date Feb 4, 2014
- Intel Corporation
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual machine control structure identification decoder
- Patent number 8,205,032
- Issue date Jun 19, 2012
- Intel Corporation
- Sanjoy K. Mondal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ensuring coherence between graphics and display domains
- Patent number 8,151,061
- Issue date Apr 3, 2012
- Intel Corporation
- Robert L. Farrell
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for decoding a virtual machine control structu...
- Patent number 7,937,525
- Issue date May 3, 2011
- Intel Corporation
- Sanjoy K. Mondal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for address generation in processors
- Patent number 7,269,711
- Issue date Sep 11, 2007
- Intel Corporation
- Rajesh B. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control word prediction and varying recovery upon comparing actual...
- Patent number 7,249,243
- Issue date Jul 24, 2007
- Intel Corporation
- Mohammad A. Abadallah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for selecting a frequency and voltage combination...
- Patent number 6,988,211
- Issue date Jan 17, 2006
- Intel Corporation
- Leslie E. Cline
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple operating frequencies in a processor
- Patent number 6,785,829
- Issue date Aug 31, 2004
- Intel Corporation
- Varghese George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating data scaling and buffering functions to minimize memory...
- Patent number 6,091,426
- Issue date Jul 18, 2000
- Intel Corporation
- Jerrold V. Hauck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for maintaining audio sample correlation
- Patent number 5,953,411
- Issue date Sep 14, 1999
- Intel Corporation
- Robert L. Farrell
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Page open/close scheme based on high order address bit and likeliho...
- Patent number 5,664,153
- Issue date Sep 2, 1997
- Intel Corporation
- Robert Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable multimedia platform architecture
- Patent number 5,640,543
- Issue date Jun 17, 1997
- Intel Corporation
- Robert Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable interrupt device and method
- Patent number 5,519,345
- Issue date May 21, 1996
- Intel Corporation
- Robert Farrell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for synchronizing clocks upon reset
- Patent number 5,510,740
- Issue date Apr 23, 1996
- Intel Corporation
- Robert Farrell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel multistage synchronization method and apparatus
- Patent number 5,488,639
- Issue date Jan 30, 1996
- Intel Corporation
- Peter D. MacWilliams
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Second level cache controller unit and system
- Patent number 5,355,467
- Issue date Oct 11, 1994
- Intel Corporation
- Peter D. MacWilliams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache subsystem for microprocessor based computer system with synch...
- Patent number 5,293,603
- Issue date Mar 8, 1994
- Intel Corporation
- Peter D. MacWilliams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory integrated circuit for use with a synchronous central...
- Patent number 5,228,134
- Issue date Jul 13, 1993
- Intel Corporation
- Peter D. MacWilliams
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS
- Publication number 20170109280
- Publication date Apr 20, 2017
- Intel Corporation
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS
- Publication number 20170109287
- Publication date Apr 20, 2017
- Intel Corporation
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS
- Publication number 20170109304
- Publication date Apr 20, 2017
- Intel Corporation
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED DEPTH BUFFER CACHE APPARATUS AND METHOD
- Publication number 20160307362
- Publication date Oct 20, 2016
- ROBERT L. FARRELL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Constant Buffer Size Multi-Sampled Anti-Aliasing Depth Compression
- Publication number 20160086374
- Publication date Mar 24, 2016
- Intel Corporation
- Robert L. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Position-Only Shading Pipeline
- Publication number 20160086299
- Publication date Mar 24, 2016
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FOUR CORNER HIGH PERFORMANCE DEPTH TEST
- Publication number 20150178982
- Publication date Jun 25, 2015
- Robert Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS
- Publication number 20140136797
- Publication date May 15, 2014
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS
- Publication number 20130207987
- Publication date Aug 15, 2013
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS
- Publication number 20130117509
- Publication date May 9, 2013
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR SAFE ENQUEUING OF EVENTS
- Publication number 20130007751
- Publication date Jan 3, 2013
- Robert L. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Page Fault Handling Mechanism
- Publication number 20120236010
- Publication date Sep 20, 2012
- Boris Ginzburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementing TLB Synchronization for Systems with Shared Virtual Me...
- Publication number 20120233439
- Publication date Sep 13, 2012
- Boris Ginzburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS
- Publication number 20120200585
- Publication date Aug 9, 2012
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtual Machine Control Structure Identification Decoder
- Publication number 20110173613
- Publication date Jul 14, 2011
- Sanjoy K. Mondal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENSURING COHERENCE BETWEEN GRAPHICS AND DISPLAY DOMAINS
- Publication number 20100235320
- Publication date Sep 16, 2010
- Robert L. Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thread ordering techniques
- Publication number 20100031268
- Publication date Feb 4, 2010
- Michael K. Dwyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Graphics processing with hidden surface removal
- Publication number 20090322747
- Publication date Dec 31, 2009
- Robert Farrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS
- Publication number 20090248983
- Publication date Oct 1, 2009
- Zeev Offen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtual machine control structure decoder
- Publication number 20050289541
- Publication date Dec 29, 2005
- Sanjoy K. Mondal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for address generation in processors
- Publication number 20050144423
- Publication date Jun 30, 2005
- Intel Corporation
- Rajesh B. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor performance state control
- Publication number 20020087896
- Publication date Jul 4, 2002
- Leslie E. Cline
- G06 - COMPUTING CALCULATING COUNTING

Robert Farrell

Person

Patents Grantslast 30 patents

Technique to share information among different cache coherency domains

Technique to share information among different cache coherency domains

Optimized depth buffer cache apparatus and method

Technique to share information among different cache coherency domains

Position-only shading pipeline

Technique to share information among different cache coherency domains

Four corner high performance depth test

Constant buffer size multi-sampled anti-aliasing depth compression

Technique to share information among different cache coherency domains

Technique to share information among different cache coherency domains

Technique to share information among different cache coherency domains

Method and system for safe enqueuing of events

Technique to share information among different cache coherency domains

Virtual machine control structure identification decoder

Ensuring coherence between graphics and display domains

Method and apparatus for decoding a virtual machine control structu...

Methods and apparatus for address generation in processors

Control word prediction and varying recovery upon comparing actual...

System and method for selecting a frequency and voltage combination...

Multiple operating frequencies in a processor

Integrating data scaling and buffering functions to minimize memory...

Method and apparatus for maintaining audio sample correlation

Page open/close scheme based on high order address bit and likeliho...

Scalable multimedia platform architecture

Reconfigurable interrupt device and method

Method for synchronizing clocks upon reset

Parallel multistage synchronization method and apparatus

Second level cache controller unit and system

Cache subsystem for microprocessor based computer system with synch...

Cache memory integrated circuit for use with a synchronous central...

Patents Applicationslast 30 patents

TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS

TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS

TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS

OPTIMIZED DEPTH BUFFER CACHE APPARATUS AND METHOD

Constant Buffer Size Multi-Sampled Anti-Aliasing Depth Compression

Position-Only Shading Pipeline

FOUR CORNER HIGH PERFORMANCE DEPTH TEST

TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS

TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS

TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS

METHOD AND SYSTEM FOR SAFE ENQUEUING OF EVENTS

Page Fault Handling Mechanism

Implementing TLB Synchronization for Systems with Shared Virtual Me...

TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS

Virtual Machine Control Structure Identification Decoder

ENSURING COHERENCE BETWEEN GRAPHICS AND DISPLAY DOMAINS

Thread ordering techniques

Graphics processing with hidden surface removal

TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS

Virtual machine control structure decoder

Methods and apparatus for address generation in processors

Processor performance state control