Robert Frickey

Person

Sacramento, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data recovery in memory devices
- Patent number 10,303,571
- Issue date May 28, 2019
- Intel Corporation
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Word line read disturb error reduction through fine grained access...
- Patent number 10,236,069
- Issue date Mar 19, 2019
- Intel Corporation
- Ning Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing redundancy information in a non-volatile memory
- Patent number 10,067,829
- Issue date Sep 4, 2018
- Intel Corporation
- Robert E. Frickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measurement and reporting of the latency of input and output operat...
- Patent number 10,025,535
- Issue date Jul 17, 2018
- Intel Corporation
- Robert E. Frickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration information backup in memory systems
- Patent number 9,817,600
- Issue date Nov 14, 2017
- Intel Corporation
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing read latency for a block erasable...
- Patent number 9,679,658
- Issue date Jun 13, 2017
- Intel Corporation
- David J. Pelster
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration information backup in memory systems
- Patent number 9,552,159
- Issue date Jan 24, 2017
- Intel Corporation
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error corrected pre-read for upper page write in a multi-level cell...
- Patent number 9,543,019
- Issue date Jan 10, 2017
- Intel Corporation
- Robert E. Frickey
- G11 - INFORMATION STORAGE
Information Patent Grant
Lower page read for multi-level cell memory
- Patent number 9,524,774
- Issue date Dec 20, 2016
- Intel Corporation
- Robert E. Frickey
- G11 - INFORMATION STORAGE
Information Patent Grant
Data integrity management in memory systems
- Patent number 9,354,973
- Issue date May 31, 2016
- Intel Corporation
- Yogesh B. Wakchaure
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lower page read for multi-level cell memory
- Patent number 9,236,136
- Issue date Jan 12, 2016
- Intel Corporation
- Robert E. Frickey
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration information backup in memory systems
- Patent number 9,183,091
- Issue date Nov 10, 2015
- Intel Corporation
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
WORD LINE READ DISTURB ERROR REDUCTION THROUGH FINE GRAINED ACCESS...
- Publication number 20190279730
- Publication date Sep 12, 2019
- Intel Corporation
- Ning WU
- G11 - INFORMATION STORAGE
Information Patent Application
DATA STORAGE DEVICE WITH DEFECTIVE DIE INDICATOR
- Publication number 20190042112
- Publication date Feb 7, 2019
- Intel Corporation
- Sarvesh Varakabe Gangadhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORD LINE READ DISTURB ERROR REDUCTION THROUGH FINE GRAINED ACCESS...
- Publication number 20180366204
- Publication date Dec 20, 2018
- Intel Corporation
- Ning WU
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION INFORMATION BACKUP IN MEMORY SYSTEMS
- Publication number 20170139631
- Publication date May 18, 2017
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA RECOVERY IN MEMORY DEVICES
- Publication number 20170123946
- Publication date May 4, 2017
- Intel Corporation
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REDUCING READ LATENCY FOR A BLOCK ERASABLE...
- Publication number 20160379715
- Publication date Dec 29, 2016
- Intel Corporation
- David J. PELSTER
- G11 - INFORMATION STORAGE
Information Patent Application
MEASUREMENT AND REPORTING OF THE LATENCY OF INPUT AND OUTPUT OPERAT...
- Publication number 20160283119
- Publication date Sep 29, 2016
- Intel Corporation
- Robert E. FRICKEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY
- Publication number 20160155497
- Publication date Jun 2, 2016
- Intel Corporation
- Robert E. Frickey
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION INFORMATION BACKUP IN MEMORY SYSTEMS
- Publication number 20160054925
- Publication date Feb 25, 2016
- Intel Corporation
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING REDUNDANCY INFORMATION IN A NON-VOLATILE MEMORY
- Publication number 20150169405
- Publication date Jun 18, 2015
- Robert E. Frickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA INTEGRITY MANAGEMENT IN MEMORY SYSTEMS
- Publication number 20140281813
- Publication date Sep 18, 2014
- Yogesh B. Wakchaure
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY
- Publication number 20140173174
- Publication date Jun 19, 2014
- Robert E. Frickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTED PRE-READ FOR UPPER PAGE WRITE IN A MULTI-LEVEL CELL...
- Publication number 20140164872
- Publication date Jun 12, 2014
- Robert E. Frickey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION INFORMATION BACKUP IN MEMORY SYSTEMS
- Publication number 20140089563
- Publication date Mar 27, 2014
- Ning Wu
- G06 - COMPUTING CALCULATING COUNTING

Robert Frickey

Person

Patents Grantslast 30 patents

Data recovery in memory devices

Word line read disturb error reduction through fine grained access...

Managing redundancy information in a non-volatile memory

Measurement and reporting of the latency of input and output operat...

Configuration information backup in memory systems

Method and apparatus for reducing read latency for a block erasable...

Configuration information backup in memory systems

Error corrected pre-read for upper page write in a multi-level cell...

Lower page read for multi-level cell memory

Data integrity management in memory systems

Lower page read for multi-level cell memory

Configuration information backup in memory systems

Patents Applicationslast 30 patents

WORD LINE READ DISTURB ERROR REDUCTION THROUGH FINE GRAINED ACCESS...

DATA STORAGE DEVICE WITH DEFECTIVE DIE INDICATOR

WORD LINE READ DISTURB ERROR REDUCTION THROUGH FINE GRAINED ACCESS...

CONFIGURATION INFORMATION BACKUP IN MEMORY SYSTEMS

DATA RECOVERY IN MEMORY DEVICES

METHOD AND APPARATUS FOR REDUCING READ LATENCY FOR A BLOCK ERASABLE...

MEASUREMENT AND REPORTING OF THE LATENCY OF INPUT AND OUTPUT OPERAT...

LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY

CONFIGURATION INFORMATION BACKUP IN MEMORY SYSTEMS

MANAGING REDUNDANCY INFORMATION IN A NON-VOLATILE MEMORY

DATA INTEGRITY MANAGEMENT IN MEMORY SYSTEMS

LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY

ERROR CORRECTED PRE-READ FOR UPPER PAGE WRITE IN A MULTI-LEVEL CELL...

CONFIGURATION INFORMATION BACKUP IN MEMORY SYSTEMS