Robert G. Southworth

Person

Chatsworth, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Receiver-based precision congestion control
- Patent number 12,074,794
- Issue date Aug 27, 2024
- Intel Corporation
- Rong Pan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cyclic redundancy check (CRC) update mechanism
- Patent number 12,052,170
- Issue date Jul 30, 2024
- Intel Corporation
- Karl S. Papadantonakis
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic virtual cut-through and dynamic fabric bandwidth allocation...
- Patent number 11,916,800
- Issue date Feb 27, 2024
- Intel Corporation
- David Arditti Ilitzky
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Maintaining bandwidth utilization in the presence of packet drops
- Patent number 11,722,438
- Issue date Aug 8, 2023
- Intel Corporation
- John Greth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-path packet descriptor delivery scheme
- Patent number 11,700,209
- Issue date Jul 11, 2023
- Intel Corporation
- Robert Southworth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for high-precision timestamping of packets
- Patent number 11,671,194
- Issue date Jun 6, 2023
- Intel Corporation
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Shared memory mesh for switching
- Patent number 11,641,326
- Issue date May 2, 2023
- Intel Corporation
- Karl S. Papadantonakis
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for adaptive network packet egress scheduling
- Patent number 11,489,789
- Issue date Nov 1, 2022
- Intel Corporation
- Carl Geoffrion
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
On-demand packet queuing in a network device
- Patent number 11,381,515
- Issue date Jul 5, 2022
- Intel Corporation
- Arvind Srinivasan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for high-precision timestamping of packets
- Patent number 11,212,024
- Issue date Dec 28, 2021
- Intel Corporation
- Mark A. Bordogna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for controlling jitter at network packet egress
- Patent number 11,108,697
- Issue date Aug 31, 2021
- Intel Corporation
- Chih-Jen Chang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies for managing exact match hash table growth
- Patent number 11,050,554
- Issue date Jun 29, 2021
- Intel Corporation
- Naru Sundar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shaping of post-scheduling network pipeline jitter
- Patent number 10,812,402
- Issue date Oct 20, 2020
- Intel Corporation
- Robert Southworth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
CRC update mechanism
- Patent number 10,785,150
- Issue date Sep 22, 2020
- Karl S. Papadantonakis
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined hash table with reduced collisions
- Patent number 10,621,080
- Issue date Apr 14, 2020
- Intel Corporation
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single-lane, twenty-five gigabit ethernet
- Patent number 9,992,125
- Issue date Jun 5, 2018
- Intel Corporation
- Alain Gravel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Single-lane, twenty-five gigabit ethernet
- Patent number 9,426,096
- Issue date Aug 23, 2016
- Intel Corporation
- Alain Gravel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable frame processing pipeline in a packet switch
- Patent number 8,571,031
- Issue date Oct 29, 2013
- Intel Corporation
- Michael Davies
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Global ports in multi-switch systems
- Patent number 8,570,856
- Issue date Oct 29, 2013
- Intel Corporation
- Robert Southworth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Global ports in multi-switch systems
- Patent number 8,098,574
- Issue date Jan 17, 2012
- Fulcrum Microsystems, Inc.
- Robert Southworth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Shared-memory switch fabric architecture
- Patent number 7,814,280
- Issue date Oct 12, 2010
- Fulcrum Microsystems Inc.
- Uri Cummings
- G11 - INFORMATION STORAGE
Information Patent Grant
Asynchronous multiple-order issue system architecture
- Patent number 7,698,535
- Issue date Apr 13, 2010
- Fulcrum Microsystems, Inc.
- Andrew Lines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for facilitating conversion between asynchronous and syn...
- Patent number 6,961,863
- Issue date Nov 1, 2005
- Fulcrum Microsystems Inc.
- Michael I. Davies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for facilitating conversion between asynchronous and syn...
- Patent number 6,950,959
- Issue date Sep 27, 2005
- Fulcrum Microystems Inc.
- Michael I. Davies
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
RECEIVER-BASED PRECISION CONGESTION CONTROL
- Publication number 20240195740
- Publication date Jun 13, 2024
- Intel Corporation
- Rong Pan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE ARCHITECTURE FOR STATEFUL DATA PLANE EVENT PROCESSING
- Publication number 20230139762
- Publication date May 4, 2023
- Intel Corporation
- Stephen IBANEZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE TRANSPORT PROTOCOL ARCHITECTURE
- Publication number 20230127722
- Publication date Apr 27, 2023
- Intel Corporation
- Stephen IBANEZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WINDOW-BASED CONGESTION CONTROL
- Publication number 20230123387
- Publication date Apr 20, 2023
- Intel Corporation
- Robert SOUTHWORTH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SELECTIVE CONGESTION NOTIFICATION BY A NETWORK INTERFACE DEVICE
- Publication number 20220210075
- Publication date Jun 30, 2022
- Intel Corporation
- Malek MUSLEH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SWITCH-ORIGINATED CONGESTION MESSAGES
- Publication number 20220124035
- Publication date Apr 21, 2022
- Intel Corporation
- Junggun LEE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TRANSMIT RATE BASED ON DETECTED AVAILABLE BANDWIDTH
- Publication number 20220103479
- Publication date Mar 31, 2022
- Intel Corporation
- Pedro YEBENES SEGURA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONGESTION CONTROL
- Publication number 20220103484
- Publication date Mar 31, 2022
- Intel Corporation
- Roberto PENARANDA CEBRIAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR HIGH-PRECISION TIMESTAMPING OF PACKETS
- Publication number 20220077946
- Publication date Mar 10, 2022
- Intel Corporation
- Mark A. BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RESOURCE CONSUMPTION CONTROL
- Publication number 20220014478
- Publication date Jan 13, 2022
- Intel Corporation
- Junggun LEE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CACHE ALLOCATION SYSTEM
- Publication number 20210359955
- Publication date Nov 18, 2021
- Intel Corporation
- Malek MUSLEH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCH-BASED ADAPTIVE TRANSFORMATION FOR EDGE APPLIANCES
- Publication number 20210320875
- Publication date Oct 14, 2021
- Francesc Guim Bernat
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR HIGH-PRECISION TIMESTAMPING OF PACKETS
- Publication number 20210203428
- Publication date Jul 1, 2021
- Intel Corporation
- Mark A. BORDOGNA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RELIABLE TRANSPORT ARCHITECTURE
- Publication number 20210119930
- Publication date Apr 22, 2021
- Intel Corporation
- Mark DEBBAGE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RECEIVER-BASED PRECISION CONGESTION CONTROL
- Publication number 20210112002
- Publication date Apr 15, 2021
- Intel Corporation
- Rong Pan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING MULTI-NODE PERFORMANCE OF MACHINE LEARNING WORKLOADS
- Publication number 20210092069
- Publication date Mar 25, 2021
- Intel Corporation
- Malek MUSLEH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAINTAINING BANDWIDTH UTILIZATION IN THE PRESENCE OF PACKET DROPS
- Publication number 20210058343
- Publication date Feb 25, 2021
- Intel Corporation
- John GRETH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TIMESTAMP-BASED FAIRNESS EGRESS FROM INGRESS QUEUES
- Publication number 20210058334
- Publication date Feb 25, 2021
- Intel Corporation
- John GRETH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SHARED MEMORY MESH FOR SWITCHING
- Publication number 20200412666
- Publication date Dec 31, 2020
- Intel Corporation
- Karl S. PAPADANTONAKIS
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CRC UPDATE MECHANISM
- Publication number 20200412649
- Publication date Dec 31, 2020
- Intel Corporation
- Karl S. Papadantonakis
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OUTPUT QUEUEING WITH SCALABILITY FOR SEGMENTED TRAFFIC IN A HIGH-RA...
- Publication number 20200412670
- Publication date Dec 31, 2020
- Intel Corporation
- David ARDITTI ILITZKY
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMIC VIRTUAL CUT-THROUGH AND DYNAMIC FABRIC BANDWIDTH ALLOCATION...
- Publication number 20200412659
- Publication date Dec 31, 2020
- Intel Corporation
- David ARDITTI ILITZKY
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PIPELINED HASH TABLE WITH REDUCED COLLISIONS
- Publication number 20200159654
- Publication date May 21, 2020
- Intel Corporation
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PATH PACKET DESCRIPTOR DELIVERY SCHEME
- Publication number 20200136986
- Publication date Apr 30, 2020
- Intel Corporation
- Robert SOUTHWORTH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR ADAPTIVE NETWORK PACKET EGRESS SCHEDULING
- Publication number 20200007470
- Publication date Jan 2, 2020
- Intel Corporation
- Carl Geoffrion
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ON-DEMAND PACKET QUEUING IN A NETWORK DEVICE
- Publication number 20190379610
- Publication date Dec 12, 2019
- Intel Corporation
- Arvind SRINIVASAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SHAPING OF POST-SCHEDULING NETWORK PIPELINE JITTER
- Publication number 20190140964
- Publication date May 9, 2019
- Robert Southworth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNOLOGIES FOR MANAGING EXACT MATCH HASH TABLE GROWTH
- Publication number 20190044859
- Publication date Feb 7, 2019
- Intel Corporation
- Naru Sundar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR CONTROLLING JITTER AT NETWORK PACKET EGRESS
- Publication number 20190044867
- Publication date Feb 7, 2019
- Intel Corporation
- Chih-Jen Chang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PIPELINED HASH TABLE WITH REDUCED COLLISIONS
- Publication number 20170286006
- Publication date Oct 5, 2017
- Sanjeev Jain
- G06 - COMPUTING CALCULATING COUNTING

Robert G. Southworth

Person

Patents Grantslast 30 patents

Receiver-based precision congestion control

Cyclic redundancy check (CRC) update mechanism

Dynamic virtual cut-through and dynamic fabric bandwidth allocation...

Maintaining bandwidth utilization in the presence of packet drops

Multi-path packet descriptor delivery scheme

Technologies for high-precision timestamping of packets

Shared memory mesh for switching

Technologies for adaptive network packet egress scheduling

On-demand packet queuing in a network device

Technologies for high-precision timestamping of packets

Technologies for controlling jitter at network packet egress

Technologies for managing exact match hash table growth

Shaping of post-scheduling network pipeline jitter

CRC update mechanism

Pipelined hash table with reduced collisions

Single-lane, twenty-five gigabit ethernet

Single-lane, twenty-five gigabit ethernet

Configurable frame processing pipeline in a packet switch

Global ports in multi-switch systems

Global ports in multi-switch systems

Shared-memory switch fabric architecture

Asynchronous multiple-order issue system architecture

Techniques for facilitating conversion between asynchronous and syn...

Techniques for facilitating conversion between asynchronous and syn...

Patents Applicationslast 30 patents

RECEIVER-BASED PRECISION CONGESTION CONTROL

PROGRAMMABLE ARCHITECTURE FOR STATEFUL DATA PLANE EVENT PROCESSING

PROGRAMMABLE TRANSPORT PROTOCOL ARCHITECTURE

WINDOW-BASED CONGESTION CONTROL

SELECTIVE CONGESTION NOTIFICATION BY A NETWORK INTERFACE DEVICE

SWITCH-ORIGINATED CONGESTION MESSAGES

TRANSMIT RATE BASED ON DETECTED AVAILABLE BANDWIDTH

CONGESTION CONTROL

TECHNOLOGIES FOR HIGH-PRECISION TIMESTAMPING OF PACKETS

RESOURCE CONSUMPTION CONTROL

CACHE ALLOCATION SYSTEM

SWITCH-BASED ADAPTIVE TRANSFORMATION FOR EDGE APPLIANCES

TECHNOLOGIES FOR HIGH-PRECISION TIMESTAMPING OF PACKETS

RELIABLE TRANSPORT ARCHITECTURE

RECEIVER-BASED PRECISION CONGESTION CONTROL

ACCELERATING MULTI-NODE PERFORMANCE OF MACHINE LEARNING WORKLOADS

MAINTAINING BANDWIDTH UTILIZATION IN THE PRESENCE OF PACKET DROPS

TIMESTAMP-BASED FAIRNESS EGRESS FROM INGRESS QUEUES

SHARED MEMORY MESH FOR SWITCHING

CRC UPDATE MECHANISM

OUTPUT QUEUEING WITH SCALABILITY FOR SEGMENTED TRAFFIC IN A HIGH-RA...

DYNAMIC VIRTUAL CUT-THROUGH AND DYNAMIC FABRIC BANDWIDTH ALLOCATION...

PIPELINED HASH TABLE WITH REDUCED COLLISIONS

MULTI-PATH PACKET DESCRIPTOR DELIVERY SCHEME

TECHNOLOGIES FOR ADAPTIVE NETWORK PACKET EGRESS SCHEDULING

ON-DEMAND PACKET QUEUING IN A NETWORK DEVICE

SHAPING OF POST-SCHEDULING NETWORK PIPELINE JITTER

TECHNOLOGIES FOR MANAGING EXACT MATCH HASH TABLE GROWTH

TECHNOLOGIES FOR CONTROLLING JITTER AT NETWORK PACKET EGRESS

PIPELINED HASH TABLE WITH REDUCED COLLISIONS