Robert Gleixner

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Triggering of stronger write pulses in a memory device based on pri...
- Patent number 12,131,778
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device architecture using multiple physical cells per bit to...
- Patent number 12,020,743
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Joseph Michael McCrate
- G11 - INFORMATION STORAGE
Information Patent Grant
Generating patterns for memory threshold voltage difference
- Patent number 11,978,513
- Issue date May 7, 2024
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Error detection and correction in memory
- Patent number 11,868,211
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Joseph M. McCrate
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicting and compensating for degradation of memory cells
- Patent number 11,823,745
- Issue date Nov 21, 2023
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-read in opposite polarity to evaluate read margin
- Patent number 11,823,761
- Issue date Nov 21, 2023
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Increase of a sense current in memory
- Patent number 11,735,258
- Issue date Aug 22, 2023
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory electrodes and formation thereof
- Patent number 11,711,987
- Issue date Jul 25, 2023
- Micron Technology, Inc.
- Joseph M. McCrate
Information Patent Grant
Write operation techniques for memory systems
- Patent number 11,710,517
- Issue date Jul 25, 2023
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Increase of a sense current in memory
- Patent number 11,705,195
- Issue date Jul 18, 2023
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Random value generator
- Patent number 11,651,825
- Issue date May 16, 2023
- Micron Technology, Inc.
- Zhongyuan Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device architecture using multiple physical cells per bit to...
- Patent number 11,605,418
- Issue date Mar 14, 2023
- Micron Technology, Inc.
- Joseph Michael McCrate
- G11 - INFORMATION STORAGE
Information Patent Grant
Read cache for reset read disturb mitigation
- Patent number 11,568,932
- Issue date Jan 31, 2023
- Micron Technology, Inc.
- Zhongyuan Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detection and correction in memory
- Patent number 11,455,210
- Issue date Sep 27, 2022
- Micron Technology, Inc.
- Joseph M. McCrate
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicting and compensating for degradation of memory cells
- Patent number 11,456,036
- Issue date Sep 27, 2022
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Increase of a sense current in memory
- Patent number 11,295,811
- Issue date Apr 5, 2022
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Write operation techniques for memory systems
- Patent number 11,244,717
- Issue date Feb 8, 2022
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Increase of a sense current in memory
- Patent number 11,211,122
- Issue date Dec 28, 2021
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Maintenance process to enhance memory endurance
- Patent number 8,036,016
- Issue date Oct 11, 2011
- Micron Technology, Inc.
- Joy Sarker
- G11 - INFORMATION STORAGE
Information Patent Grant
Wirebond structure and method to connect to a microelectronic die
- Patent number 7,855,103
- Issue date Dec 21, 2010
- Intel Corporation
- Robert J. Gleixner
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Wirebond structure and method to connect to a microelectronic die
- Patent number 7,393,772
- Issue date Jul 1, 2008
- Intel Corporation
- Robert J. Gleixner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wirebond structure and method to connect to a microelectronic die
- Patent number 6,924,554
- Issue date Aug 2, 2005
- Intel Corporation
- Robert J. Gleixner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wirebond structure and method to connect to a microelectronic die
- Patent number 6,683,383
- Issue date Jan 27, 2004
- Intel Corporation
- Robert J. Gleixner
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TRIGGERING OF STRONGER WRITE PULSES IN A MEMORY DEVICE BASED ON PRI...
- Publication number 20250046373
- Publication date Feb 6, 2025
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO...
- Publication number 20240339149
- Publication date Oct 10, 2024
- Micron Technology, Inc.
- Joseph Michael McCrate
- G11 - INFORMATION STORAGE
Information Patent Application
TRIGGERING OF STRONGER WRITE PULSES IN A MEMORY DEVICE BASED ON PRI...
- Publication number 20240071491
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
GENERATING PATTERNS FOR MEMORY THRESHOLD VOLTAGE DIFFERENCE
- Publication number 20230268006
- Publication date Aug 24, 2023
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO...
- Publication number 20230215489
- Publication date Jul 6, 2023
- Micron Technology, Inc.
- Joseph Michael McCrate
- G11 - INFORMATION STORAGE
Information Patent Application
PRE-READ IN OPPOSITE POLARITY TO EVALUATE READ MARGIN
- Publication number 20230207037
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
PREDICTING AND COMPENSATING FOR DEGRADATION OF MEMORY CELLS
- Publication number 20230012598
- Publication date Jan 19, 2023
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR DETECTION AND CORRECTION IN MEMORY
- Publication number 20230014459
- Publication date Jan 19, 2023
- Micron Technology, Inc.
- Joseph M. McCrate
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RANDOM VALUE GENERATOR
- Publication number 20220328104
- Publication date Oct 13, 2022
- Micron Technology, Inc.
- Zhongyuan Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTING AND COMPENSATING FOR DEGRADATION OF MEMORY CELLS
- Publication number 20220319613
- Publication date Oct 6, 2022
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
READ CACHE FOR RESET READ DISTURB MITIGATION
- Publication number 20220270679
- Publication date Aug 25, 2022
- Micron Technology, Inc.
- Zhongyuan Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASE OF A SENSE CURRENT IN MEMORY
- Publication number 20220223203
- Publication date Jul 14, 2022
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE OPERATION TECHNIQUES FOR MEMORY SYSTEMS
- Publication number 20220130444
- Publication date Apr 28, 2022
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE ARCHITECTURE USING MULTIPLE CELLS PER BIT
- Publication number 20220130447
- Publication date Apr 28, 2022
- Micron Technology, Inc.
- Joseph Michael McCrate
- G11 - INFORMATION STORAGE
Information Patent Application
INCREASE OF A SENSE CURRENT IN MEMORY
- Publication number 20220108746
- Publication date Apr 7, 2022
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ELECTRODES AND FORMATION THEREOF
- Publication number 20220069207
- Publication date Mar 3, 2022
- Micron Technology, Inc.
- Joseph M. McCrate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INCREASE OF A SENSE CURRENT IN MEMORY
- Publication number 20220068377
- Publication date Mar 3, 2022
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE OPERATION TECHNIQUES FOR MEMORY SYSTEMS
- Publication number 20210166746
- Publication date Jun 3, 2021
- Micron Technology, Inc.
- Zhongyuan Lu
- G11 - INFORMATION STORAGE
Information Patent Application
MAINTENANCE PROCESS TO ENHANCE MEMORY ENDURANCE
- Publication number 20110051507
- Publication date Mar 3, 2011
- Joy Sarkar
- G11 - INFORMATION STORAGE
Information Patent Application
Chalcogenide anti-fuse
- Publication number 20090180313
- Publication date Jul 16, 2009
- Wim Deweerd
- G11 - INFORMATION STORAGE
Information Patent Application
WIREBOND STRUCTURE AND METHOD TO CONNECT TO A MICROELECTRONIC DIE
- Publication number 20080227285
- Publication date Sep 18, 2008
- ROBERT J. GLEIXNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wirebond structure and method to connect to a microelectronic die
- Publication number 20050079651
- Publication date Apr 14, 2005
- Robert J. Gleixner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wirebond structure and method to connect to a microelectronic die
- Publication number 20030205827
- Publication date Nov 6, 2003
- Intel Corporation
- Robert J. Gleixner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wirebond structure and method to connect to a microelectronic die
- Publication number 20030075804
- Publication date Apr 24, 2003
- Intel Corporation
- Robert J. Gleixner
- H01 - BASIC ELECTRIC ELEMENTS

Robert Gleixner

Person

Patents Grantslast 30 patents

Triggering of stronger write pulses in a memory device based on pri...

Memory device architecture using multiple physical cells per bit to...

Generating patterns for memory threshold voltage difference

Error detection and correction in memory

Predicting and compensating for degradation of memory cells

Pre-read in opposite polarity to evaluate read margin

Increase of a sense current in memory

Memory electrodes and formation thereof

Write operation techniques for memory systems

Increase of a sense current in memory

Random value generator

Memory device architecture using multiple physical cells per bit to...

Read cache for reset read disturb mitigation

Error detection and correction in memory

Predicting and compensating for degradation of memory cells

Increase of a sense current in memory

Write operation techniques for memory systems

Increase of a sense current in memory

Maintenance process to enhance memory endurance

Wirebond structure and method to connect to a microelectronic die

Wirebond structure and method to connect to a microelectronic die

Wirebond structure and method to connect to a microelectronic die

Wirebond structure and method to connect to a microelectronic die

Patents Applicationslast 30 patents

TRIGGERING OF STRONGER WRITE PULSES IN A MEMORY DEVICE BASED ON PRI...

MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO...

TRIGGERING OF STRONGER WRITE PULSES IN A MEMORY DEVICE BASED ON PRI...

GENERATING PATTERNS FOR MEMORY THRESHOLD VOLTAGE DIFFERENCE

MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO...

PRE-READ IN OPPOSITE POLARITY TO EVALUATE READ MARGIN

PREDICTING AND COMPENSATING FOR DEGRADATION OF MEMORY CELLS

ERROR DETECTION AND CORRECTION IN MEMORY

RANDOM VALUE GENERATOR

PREDICTING AND COMPENSATING FOR DEGRADATION OF MEMORY CELLS

READ CACHE FOR RESET READ DISTURB MITIGATION

INCREASE OF A SENSE CURRENT IN MEMORY

WRITE OPERATION TECHNIQUES FOR MEMORY SYSTEMS

MEMORY DEVICE ARCHITECTURE USING MULTIPLE CELLS PER BIT

INCREASE OF A SENSE CURRENT IN MEMORY

MEMORY ELECTRODES AND FORMATION THEREOF

INCREASE OF A SENSE CURRENT IN MEMORY

WRITE OPERATION TECHNIQUES FOR MEMORY SYSTEMS

MAINTENANCE PROCESS TO ENHANCE MEMORY ENDURANCE

Chalcogenide anti-fuse

WIREBOND STRUCTURE AND METHOD TO CONNECT TO A MICROELECTRONIC DIE

Wirebond structure and method to connect to a microelectronic die

Wirebond structure and method to connect to a microelectronic die

Wirebond structure and method to connect to a microelectronic die