Robert Hinton

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-level tracking of in-use state of cache lines
- Patent number 9,348,591
- Issue date May 24, 2016
- Intel Corporation
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hiding instruction cache miss latency by running tag lookups ahead...
- Patent number 9,158,696
- Issue date Oct 13, 2015
- Intel Corporation
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for partitioned pipelined execution of multipl...
- Patent number 9,146,745
- Issue date Sep 29, 2015
- Intel Corporation
- Stephan Jourdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoupling the number of logical threads from the number of simulta...
- Patent number 7,797,683
- Issue date Sep 14, 2010
- Intel Corporation
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Overriding a static prediction with a level-two predictor
- Patent number 7,533,252
- Issue date May 12, 2009
- Intel Corporation
- Mark C. Davis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for partitioned pipelined fetching of multiple...
- Patent number 7,454,596
- Issue date Nov 18, 2008
- Intel Corporation
- Stephan Jourdan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIDING INSTRUCTION CACHE MISS LATENCY BY RUNNING TAG LOOKUPS AHEAD...
- Publication number 20140229677
- Publication date Aug 14, 2014
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL TRACKING OF IN-USE STATE OF CACHE LINES
- Publication number 20130275733
- Publication date Oct 17, 2013
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Predicting instruction branches with bimodal, little global, big gl...
- Publication number 20080072024
- Publication date Mar 20, 2008
- Mark C. Davis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Overriding a static prediction
- Publication number 20080059779
- Publication date Mar 6, 2008
- Mark C. Davis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for partitioned pipelined execution of multipl...
- Publication number 20080005544
- Publication date Jan 3, 2008
- Stephan Jourdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for partitioned pipelined fetching of multiple...
- Publication number 20080005534
- Publication date Jan 3, 2008
- Stephan Jourdan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Decoupling the number of logical threads from the number of simulta...
- Publication number 20050193278
- Publication date Sep 1, 2005
- Intel Corporation
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to control steering of instruction streams
- Publication number 20050149696
- Publication date Jul 7, 2005
- Robert L. Hinton
- G06 - COMPUTING CALCULATING COUNTING

Robert Hinton

Person

Patents Grantslast 30 patents

Multi-level tracking of in-use state of cache lines

Hiding instruction cache miss latency by running tag lookups ahead...

Method and apparatus for partitioned pipelined execution of multipl...

Decoupling the number of logical threads from the number of simulta...

Overriding a static prediction with a level-two predictor

Method and apparatus for partitioned pipelined fetching of multiple...

Patents Applicationslast 30 patents

HIDING INSTRUCTION CACHE MISS LATENCY BY RUNNING TAG LOOKUPS AHEAD...

MULTI-LEVEL TRACKING OF IN-USE STATE OF CACHE LINES

Predicting instruction branches with bimodal, little global, big gl...

Overriding a static prediction

Method and apparatus for partitioned pipelined execution of multipl...

Method and apparatus for partitioned pipelined fetching of multiple...

Decoupling the number of logical threads from the number of simulta...

Method and apparatus to control steering of instruction streams