Robert J. Murray

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Pulsed circuit topology to perform a memory array write operation
- Patent number 6,567,337
- Issue date May 20, 2003
- Intel Corporation
- Milo D. Sprague
- G11 - INFORMATION STORAGE
Information Patent Grant
Reset first latching mechanism for pulsed circuit topologies
- Patent number 6,542,006
- Issue date Apr 1, 2003
- Intel Corporation
- Milo D. Sprague
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulsed circuit topology including a pulsed, domino flip-flop
- Patent number 6,496,038
- Issue date Dec 17, 2002
- Intel Corporation
- Milo D. Sprague
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiported bypass cache in a bypass network
- Patent number 6,000,016
- Issue date Dec 7, 1999
- Intel Corporation
- Steve Curtis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comparator utilizing redundancy
- Patent number 5,881,076
- Issue date Mar 9, 1999
- Intel Corporation
- Robert J. Murray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory arrays with integrated bit line voltage stabilization circuitry
- Patent number 5,844,852
- Issue date Dec 1, 1998
- Intel Corporation
- Robert J. Murray
- G11 - INFORMATION STORAGE
Information Patent Grant
Latching mechanism for pulsed domino logic with inherent race margi...
- Patent number 5,796,282
- Issue date Aug 18, 1998
- Intel Corporation
- Milo David Sprague
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for implementing a single clock cycle line rep...
- Patent number 5,526,510
- Issue date Jun 11, 1996
- Intel Corporation
- Haitham Akkary
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
High throughput modular pipelined memory array
- Publication number 20040059874
- Publication date Mar 25, 2004
- Intel Corporation
- Robert James Murray
- G06 - COMPUTING CALCULATING COUNTING

Robert J. Murray

Person

Patents Grantslast 30 patents

Pulsed circuit topology to perform a memory array write operation

Reset first latching mechanism for pulsed circuit topologies

Pulsed circuit topology including a pulsed, domino flip-flop

Multiported bypass cache in a bypass network

Comparator utilizing redundancy

Memory arrays with integrated bit line voltage stabilization circuitry

Latching mechanism for pulsed domino logic with inherent race margi...

Method and apparatus for implementing a single clock cycle line rep...

Patents Applicationslast 30 patents

High throughput modular pipelined memory array