Robert J. Palermo

Person

Shoreview, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transistor-level timing analysis using embedded simulation
- Patent number 7,647,220
- Issue date Jan 12, 2010
- Cadence Design Systems, Inc.
- Pawan Kulshreshtha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for timing abstraction of digital logic circuits
- Patent number 6,877,143
- Issue date Apr 5, 2005
- Cadence Design Systems, Inc.
- Robert J Palermo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for performing improved timing analysis on vir...
- Patent number 6,760,894
- Issue date Jul 6, 2004
- Cadence Design Systems, Inc.
- Hakan Yalcin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for timing abstraction of digital logic circuits
- Patent number 6,442,739
- Issue date Aug 27, 2002
- Cadence Design Systems, Inc.
- Robert J. Palermo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of compacting data representations of hierarchical logic des...
- Patent number 5,831,869
- Issue date Nov 3, 1998
- Unisys Corporation
- Clive Robert Ellis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic timing analysis for multiple-clock designs
- Patent number 5,761,097
- Issue date Jun 2, 1998
- Unisys Corporation
- Robert J. Palermo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing drive strength adjust optimizat...
- Patent number 5,724,250
- Issue date Mar 3, 1998
- Unisys Corporation
- Joseph P. Kerzman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Functional timing analysis for characterization of virtual componen...
- Publication number 20030140324
- Publication date Jul 24, 2003
- Hakan Yalcin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transistor-level timing analysis using embedded simulation
- Publication number 20030115035
- Publication date Jun 19, 2003
- Pawan Kulshreshtha
- G06 - COMPUTING CALCULATING COUNTING

Robert J. Palermo

Person

Patents Grantslast 30 patents

Transistor-level timing analysis using embedded simulation

System and method for timing abstraction of digital logic circuits

Method and mechanism for performing improved timing analysis on vir...

System and method for timing abstraction of digital logic circuits

Method of compacting data representations of hierarchical logic des...

Logic timing analysis for multiple-clock designs

Method and apparatus for performing drive strength adjust optimizat...

Patents Applicationslast 30 patents

Functional timing analysis for characterization of virtual componen...

Transistor-level timing analysis using embedded simulation