Robert J. Royer, Jr.

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Delta checkpoints for a non-volatile memory indirection table
- Patent number 8,312,326
- Issue date Nov 13, 2012
- Intel Corporation
- Robert J. Royer, Jr.
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Cache write integrity logging
- Patent number 8,244,970
- Issue date Aug 14, 2012
- Intel Corporation
- Robert J. Royer, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache write integrity logging
- Patent number 7,937,524
- Issue date May 3, 2011
- Intel Corporation
- Robert J. Royer, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delta checkpoints for a non-volatile memory indirection table
- Patent number 7,925,925
- Issue date Apr 12, 2011
- Intel Corporation
- Robert J. Royer, Jr.
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Dynamic master/slave configuration for multiple expansion modules
- Patent number 7,587,717
- Issue date Sep 8, 2009
- Intel Corporation
- John I. Garney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining disk cache coherency in multiple operating system envir...
- Patent number 7,558,911
- Issue date Jul 7, 2009
- Intel Corporation
- John I. Garney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface for a block addressable mass storage system
- Patent number 7,328,304
- Issue date Feb 5, 2008
- Intel Corporation
- Robert J. Royer, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining cache integrity by recording write addresses in a log
- Patent number 7,299,379
- Issue date Nov 20, 2007
- Intel Corporation
- Robert J. Royer, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic master/slave configuration for multiple expansion modules
- Patent number 7,152,125
- Issue date Dec 19, 2006
- Intel Corporation
- John I. Garney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to generate cache data
- Patent number 7,103,724
- Issue date Sep 5, 2006
- Intel Corporation
- Robert J Royer, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimally mapping a memory device
- Patent number 7,089,394
- Issue date Aug 8, 2006
- Intel Corporation
- Robert J. Royer, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transportation of main memory and intermediate memory contents
- Patent number 7,085,878
- Issue date Aug 1, 2006
- Intel Corporation
- Robert J. Royer, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficient command queuing within a serial...
- Patent number 6,917,992
- Issue date Jul 12, 2005
- Intel Corporation
- Knut S. Grimsrud
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system to cache metadata
- Patent number 6,839,812
- Issue date Jan 4, 2005
- Intel Corporation
- Robert J. Royer, Jr.
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DRIVE ASSISTED SYSTEM CHECKPOINTING
- Publication number 20120173794
- Publication date Jul 5, 2012
- Robert J. Royer, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELTA CHECKPOINTS FOR A NON-VOLATILE MEMORY INDIRECTION TABLE
- Publication number 20110276827
- Publication date Nov 10, 2011
- Robert J. Royer, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE WRITE INTEGRITY LOGGING
- Publication number 20110238918
- Publication date Sep 29, 2011
- Robert J. Royer, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPURPOSING NAND READY/BUSY PIN AS COMPLETION INTERRUPT
- Publication number 20110153914
- Publication date Jun 23, 2011
- Amber D. Huffman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR MANAGING A NAND FLASH MEMORY
- Publication number 20100332730
- Publication date Dec 30, 2010
- Robert J. Royer, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELTA CHECKPOINTS FOR A NON-VOLATILE MEMORY INDIRECTION TABLE
- Publication number 20100169710
- Publication date Jul 1, 2010
- Robert J. Royer, JR.
- G06 - COMPUTING CALCULATING COUNTING

Robert J. Royer, Jr.

Person

Patents Grantslast 30 patents

Delta checkpoints for a non-volatile memory indirection table

Cache write integrity logging

Cache write integrity logging

Delta checkpoints for a non-volatile memory indirection table

Dynamic master/slave configuration for multiple expansion modules

Maintaining disk cache coherency in multiple operating system envir...

Interface for a block addressable mass storage system

Maintaining cache integrity by recording write addresses in a log

Dynamic master/slave configuration for multiple expansion modules

Method and apparatus to generate cache data

Optimally mapping a memory device

Transportation of main memory and intermediate memory contents

Method and apparatus for efficient command queuing within a serial...

Method and system to cache metadata

Patents Applicationslast 30 patents

DRIVE ASSISTED SYSTEM CHECKPOINTING

DELTA CHECKPOINTS FOR A NON-VOLATILE MEMORY INDIRECTION TABLE

CACHE WRITE INTEGRITY LOGGING

REPURPOSING NAND READY/BUSY PIN AS COMPLETION INTERRUPT

METHOD AND SYSTEM FOR MANAGING A NAND FLASH MEMORY

DELTA CHECKPOINTS FOR A NON-VOLATILE MEMORY INDIRECTION TABLE