Robert J. Stoll

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hierarchical staging areas for scheduling threads for execution
- Patent number 10,489,200
- Issue date Nov 26, 2019
- NVIDIA Corporation
- Olivier Giroux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Approach for a configurable phase-based priority scheduler
- Patent number 10,346,212
- Issue date Jul 9, 2019
- NVIDIA Corporation
- Jack Hilaire Choquette
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative execution and rollback
- Patent number 9,830,158
- Issue date Nov 28, 2017
- NVIDIA Corporation
- Jack Hilaire Choquette
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for scheduling instructions using pre-decode...
- Patent number 9,798,548
- Issue date Oct 24, 2017
- NVIDIA Corporation
- Jack Hilaire Choquette
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reordering buffer for memory access locality
- Patent number 9,798,544
- Issue date Oct 24, 2017
- NVIDIA Corporation
- Olivier Giroux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for resolving thread divergences
- Patent number 9,606,808
- Issue date Mar 28, 2017
- NVIDIA Corporation
- Jack Choquette
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and processor that include an implementation of decoupled pi...
- Patent number 9,471,307
- Issue date Oct 18, 2016
- NVIDIA Corporation
- Olivier Giroux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Credit-based streaming multiprocessor warp scheduling
- Patent number 9,189,242
- Issue date Nov 17, 2015
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Approach for a configurable phase-based priority scheduler
- Patent number 8,949,841
- Issue date Feb 3, 2015
- NVIDIA Corporation
- Jack Hilaire Choquette
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread group scheduler for computing on a parallel thread processor
- Patent number 8,732,713
- Issue date May 20, 2014
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache miss processing using a defer/replay mechanism
- Patent number 8,266,383
- Issue date Sep 11, 2012
- NVIDIA Corporation
- Alexander L. Minkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Color-compression using automatic reduction of multi-sampled pixels
- Patent number 8,233,004
- Issue date Jul 31, 2012
- NVIDIA Corporation
- Steven E Molnar
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Processing pipeline with latency bypass
- Patent number 8,125,489
- Issue date Feb 28, 2012
- NVIDIA Corporation
- Peter B. Holmqvist
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Asynchronous reorder buffer
- Patent number 7,791,611
- Issue date Sep 7, 2010
- NVIDIA Corporation
- Peter Holmqvist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for storing states used to configure a processing...
- Patent number 7,725,688
- Issue date May 25, 2010
- NVIDIA Corporation
- Robert J. Stoll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Color-compression using automatic reduction of multi-sampled pixels
- Patent number 7,692,659
- Issue date Apr 6, 2010
- NVIDIA Corporation
- Steven E Molnar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER
- Publication number 20170192822
- Publication date Jul 6, 2017
- NVIDIA Corporation
- Jack Hilaire CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER
- Publication number 20160224386
- Publication date Aug 4, 2016
- NVIDIA Corporation
- Jack Hilaire CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND PROCESSOR THAT INCLUDE AN IMPLEMENTATION OF DECOUPLED PI...
- Publication number 20150193272
- Publication date Jul 9, 2015
- NVIDIA Corporation
- Olivier Giroux
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL STAGING AREAS FOR SCHEDULING THREADS FOR EXECUTION
- Publication number 20150113538
- Publication date Apr 23, 2015
- NVIDIA Corporation
- Olivier GIROUX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER
- Publication number 20140189698
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Jack Hilaire CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REORDERING BUFFER FOR MEMORY ACCESS LOCALITY
- Publication number 20140164743
- Publication date Jun 12, 2014
- NVIDIA Corporation
- Olivier GIROUX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Resolving Thread Divergences
- Publication number 20130179662
- Publication date Jul 11, 2013
- Jack CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS USING PRE-DECODE...
- Publication number 20130166881
- Publication date Jun 27, 2013
- Jack Hilaire CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS WITHOUT INSTRUCTI...
- Publication number 20130166882
- Publication date Jun 27, 2013
- Jack Hilaire CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE EXECUTION AND ROLLBACK
- Publication number 20130117541
- Publication date May 9, 2013
- Jack Hilaire CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR
- Publication number 20120110586
- Publication date May 3, 2012
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Credit-Based Streaming Multiprocessor Warp Scheduling
- Publication number 20110072244
- Publication date Mar 24, 2011
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING

Robert J. Stoll

Person

Patents Grantslast 30 patents

Hierarchical staging areas for scheduling threads for execution

Approach for a configurable phase-based priority scheduler

Speculative execution and rollback

Methods and apparatus for scheduling instructions using pre-decode...

Reordering buffer for memory access locality

Method and system for resolving thread divergences

System and processor that include an implementation of decoupled pi...

Credit-based streaming multiprocessor warp scheduling

Approach for a configurable phase-based priority scheduler

Thread group scheduler for computing on a parallel thread processor

Cache miss processing using a defer/replay mechanism

Color-compression using automatic reduction of multi-sampled pixels

Processing pipeline with latency bypass

Asynchronous reorder buffer

System and method for storing states used to configure a processing...

Color-compression using automatic reduction of multi-sampled pixels

Patents Applicationslast 30 patents

APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER

APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER

SYSTEM AND PROCESSOR THAT INCLUDE AN IMPLEMENTATION OF DECOUPLED PI...

HIERARCHICAL STAGING AREAS FOR SCHEDULING THREADS FOR EXECUTION

APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER

REORDERING BUFFER FOR MEMORY ACCESS LOCALITY

Method and System for Resolving Thread Divergences

METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS USING PRE-DECODE...

METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS WITHOUT INSTRUCTI...

SPECULATIVE EXECUTION AND ROLLBACK

THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR

Credit-Based Streaming Multiprocessor Warp Scheduling